Fpga Tx Interface; Functional Description - Xilinx Virtex-6 FPGA User Manual

Transmitter
This chapter describes how to configure and use each of the functional blocks inside the
GTH transmitter (TX). Each GTH transceiver in the GTH Quad includes an independent
transmitter, which consists of a PCS and a PMA.
The key elements within the GTH TX are:
•
•
•
•
•
•
•

FPGA TX Interface

Functional Description

The FPGA TX interface is the FPGA's gateway to the TX datapath of the GTH transceiver.
Applications transmit data through the GTH transceiver by writing data to the TXDATA
port on the positive edge of TXUSERCLKIN. The width of the port can be configured
depending on the mode chosen (see
Table 3-1: FPGA TX Interface Port Width
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
FPGA TX Interface, page 75
TX 8B/10B Block, page 82
TX 64B/66B Block, page 86
TX Raw Mode, page 89
TX Pattern Generator, page 93
TX Polarity Control, page 96
TX Configurable Driver, page 97
Mode
8B/10B mode • 16 bits
• 32 bits
• 64 bits
64B/66B mode • 64 bits
Raw mode • 16 bits
• 20 bits
• 32 bits
• 40 bits
• 64 bits
• 80 bits
www.xilinx.com
Table 3-1).
Port Width
Chapter 3
75