Figure 2-14: Flow Chart Of Tx Reset Sequence Where Tx Buffer Is Used - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
Below are the steps describing the flow chart in
1.
2.
86
TX_SYSTEM_RESET
system_reset==0
TX_PMA_RESET
TXPMARESET==1 for
3 TXUSRCLK cycles
TX_WAIT_LOCK
tx_usrclk_stable==1 && TXLOCK==1
TXLOCK==0
TX_PCS_RESET
TXRESET==1 for
3 TXUSRCLK cycles
TXLOCK==0
TX_WAIT_PCS
5 TXUSRCLK cycles
TXLOCK==0
TX_ALMOST_READY
TXBUFERR==0 && TXLOCK==1
for 64 TXUSRCLK cycles
TXLOCK==0
TX_READY

Figure 2-14: Flow Chart of TX Reset Sequence Where TX Buffer Is Used

TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET
state.
TXPMARESET == 0
TXRESET == 0
TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles.
TXPMARESET == 1
TXRESET == X
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tx_pcs_reset_cnt==16 &&
TXBUFERR==1 &&
TXLOCK==1
tx_pcs_reset_cnt < 16 && TXBUFERR==1 && TXLOCK==1
TXBUFERR==1 && TXLOCK==1
Figure 2-14:
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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ug076_ch2_15_060606