Fabric Interface (Buffers); Overview: Transmitter And Elastic (Receiver) Buffers; Transmitter Buffer (Fifo); Receiver Buffer - Xilinx RocketIO User Manual

Fabric Interface (Buffers)

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Fabric Interface (Buffers)

Overview: Transmitter and Elastic (Receiver) Buffers

Both the transmitter and the receiver include buffers (FIFOs) in the data path. This section gives the
reasons for including the buffers and outlines their operation.

Transmitter Buffer (FIFO)

The transmitter buffer's write pointer (TXUSRCLK) is frequency-locked to its read pointer
(REFCLK). Therefore, clock correction and channel bonding are not required. The purpose of the
transmitter's buffer is to accommodate a phase difference between TXUSRCLK and REFCLK.
Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequency-
locked to the reference clock (REFCLK). Phase variations of up to one clock cycle are allowable. A
simple FIFO suffices for this purpose. A FIFO depth of four permits reliable operation with simple
detection of overflow or underflow, which might occur if the clocks are not frequency-locked.
Overflow or underflow conditions are detected and signaled at the interface.

Receiver Buffer

The receiver buffer is required for two reasons:
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The receiver uses an elastic buffer, where "elastic" refers to the ability to modify the read pointer for
clock correction and channel bonding.

Ports and Attributes

TXBUFERR

When High, this port indicates that a transmit buffer underflow or overflow has occurred. Once set
High, TXRESET must be asserted to clear this bit.

TX_BUFFER_USE

This attribute allows the user to bypass the transmit buffer. A value of FALSE bypasses the buffer,
while a TRUE keeps the buffer in the data path. This attribute should always be set to TRUE.

RXBUFSTATUS

This 2-bit port indicates the status of the receiver elastic buffer. RXBUFSTATUS[1] High indicates
if an overflow/underflow error has occurred. (Once set High, the assertion of RXRESET or
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
The RocketIO transceiver does not compute the 16-bit variant CRC used for Infiniband, and
thus does not fulfill the Infiniband CRC requirement. Infiniband CRC can be computed in the
FPGA fabric.
All CRC formats have minimum allowable packet sizes. These limits are larger than those set
by the user mode, and are defined by the specific protocol.
To accommodate the slight difference in frequency between the recovered clock RXRECCLK
and the internal FPGA core clock RXUSRCLK (clock correction)
To allow realignment of the input stream to ensure proper alignment of data being read through
multiple transceivers (channel bonding)
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