Clock And Data Recovery; Transmitter; Fpga Transmit Interface; 8B/10B Encoder - Xilinx RocketIO User Manual

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Clock and Data Recovery

The clock/data recovery (CDR) circuits lock to the reference clock automatically if the data
is not present. For proper operation, frequency variations of REFCLK, TXUSRCLK,
RXUSRCLK, and the incoming stream (RXRECCLK) must not exceed
It is critical to keep power supply noise low in order to minimize common and differential
noise modes into the clock/data recovery circuitry. See
page

Transmitter

FPGA Transmit Interface

The FPGA can send either one, two, or four characters of data to the transmitter. Each
character can be either 8 bits or 10 bits wide. If 8-bit data is applied, the additional inputs
become control signals for the 8B/10B encoder. When the 8B/10B encoder is bypassed, the
10-bit character order is:
Refer to
character.

8B/10B Encoder

A bypassable 8B/10B encoder is included. The encoder uses the same 256 data characters
and 12 control characters that are used for Gigabit Ethernet, XAUI, Fibre Channel, and
InfiniBand.
The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits per
character applied. If the K-character signal is High, the data is encoded into one of the 12
possible K-characters available in the 8B/10B code. If the K-character input is Low, the 8
bits are encoded as standard data. If the K-character input is High, and a user applies other
than one of the 12 possible combinations, TXKERR indicates the error.

Disparity Control

The 8B/10B encoder is initialized with a negative running disparity.
TXRUNDISP signals the transmitter's current running disparity.
Bits TXCHARDISPMODE and TXCHARDISPVAL control the generation of running
disparity before each byte, as shown in

Table 2-5: Running Disparity Control

For example, the transceiver can generate the sequence
or
18
89, for more details.
TXCHARDISPMODE[0]
TXCHARDISPVAL[0]
TXDATA[7:0]
Figure 3-10, page
{txchardispmode,
txchardispval}
00 Maintain running disparity normally
Invert normally generated running disparity before
01
encoding this byte
10 Set negative running disparity before encoding this byte
11 Set positive running disparity before encoding this byte
K28.5+ K28.5+ K28.5– K28.5–
K28.5– K28.5– K28.5+ K28.5+
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Chapter 2: RocketIO Transceiver Overview
59, for a graphical representation of the transmitted 10-bit
Table 2-5.
Function
1-800-255-7778
±
100 ppm.
PCB Design Requirements,
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide