Data Path Latency; Reset/Power Down - Xilinx RocketIO User Manual

Product Not Recommended for New Designs

Reset/Power Down

Data Path Latency

With the many configurations of the MGT, the both transmit and receive data path
latencies vary. Below are several tables that provide approximate latencies for common
configurations.
Table 2-6: Latency through Various Transmitter Components/Processes
Component/Process
TX Fabric/GT Interface
included
TX CRC
bypassed
included
8B/10B Encoder
bypassed
TX FIFO
TX SERDES
Table 2-7: Latency through Various Receiver Components/Processes
Component/Process
RX SERDES
Comma Detect/Realignment
included
8B/10B Decoder
bypassed
RX FIFO
RX GT/Fabric Interface
Reset/Power Down
The receiver and transmitter have their own synchronous reset inputs. The transmitter
reset recenters the transmission FIFO, and resets all transmitter registers and the 8B/10B
encoder. The receiver reset recenters the receiver elastic buffer, and resets all receiver
registers and the 8B/10B decoder. Neither reset signal has any effect on the PLLs.
After the DCM-locked signal is asserted, the resets can be asserted. The resets must be
asserted for two USRCLK2 cycles to ensure correct initialization of the FIFOs. Although
both the transmit and receive resets can be attached to the same signal, separate signals are
preferred. This allows the elastic buffer to be cleared in case of an over/underflow without
affecting the ongoing TX transmission. The following example is an implementation that
resets all three data-width transceivers.
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
1 Byte Data Path:
2.5 TXUSRCLK2 cycles
1.25 TXUSRCLK cycles
7 TXUSRCLK cycles
1 TXUSRCLK cycle
1 TXUSRCLK cycle
1 TXUSRCLK cycle
±
4 TXUSRCLK cycles ( 0.5)
SERDES_10B = FALSE:
1.5 TXUSRCLK cycles
1.5 recovered clock (RXRECCLK) cycles
2.5 or 3.5 recovered clock cycles
(some bits bypass one register, depending on comma alignment)
1 recovered clock cycle
1 recovered clock cycle
±
18 RXUSRCLK cycles ( 0.5)
1 Byte Data Path:
2.5 RXUSRCLK2 cycles
1.25 RXUSRCLK cycles
www.xilinx.com
Latency
2 Byte Data Path:
1 TXUSRCLK2 cycle
1 TXUSRCLK cycle
SERDES_10B = TRUE:
0.5 TXUSRCLK cycles (approx.)
Latency
2 Byte Data Path:
1 RXUSRCLK2 cycle
1 RXUSRCLK cycle
R
4 Byte Data Path:
1.25 TXUSRCLK2 cycles
2.5 TXUSRCLK cycles
4 Byte Data Path:
1.25 RXUSRCLK2 cycles
2.5 RXUSRCLK cycles
57