Reset/Power Down - Xilinx RocketIO User Manual

R
Table 2-6: Latency through Various Transmitter Components/Processes (Continued)
Component/Process
TX FIFO
TX SERDES
Table 2-7: Latency through Various Receiver Components/Processes
Component/Process
RX SERDES
Comma Detect/Realignment
included
8B/10B Decoder
bypassed
RX FIFO
RX GT/Fabric Interface

Reset/Power Down

The receiver and transmitter have their own synchronous reset inputs. The transmitter reset recenters
the transmission FIFO, and resets all transmitter registers and the 8B/10B encoder. The receiver
reset recenters the receiver elastic buffer, and resets all receiver registers and the 8B/10B decoder.
Neither reset signal has any effect on the PLLs.
After the DCM-locked signal is asserted, the resets can be asserted. The resets must be asserted for
two USRCLK2 cycles to ensure correct initialization of the FIFOs. Although both the transmit and
receive resets can be attached to the same signal, separate signals are preferred. This allows the
elastic buffer to be cleared in case of an over/underflow without affecting the ongoing TX
transmission. The following example is an implementation that resets all three data-width
transceivers.
Additional reset and power control descriptions are given in
Table 2-8: Reset and Power Control Descriptions
58
4 TXUSRCLK cycles (
SERDES_10B = FALSE:
1.5 TXUSRCLK cycles
1.5 recovered clock (RXRECCLK) cycles
2.5 or 3.5 recovered clock cycles
(some bits bypass one register, depending on comma alignment)
1 recovered clock cycle
1 recovered clock cycle
18 RXUSRCLK cycles (
1 Byte Data Path:
2.5 RXUSRCLK2 cycles
1.25 RXUSRCLK cycles
Ports
RXRESET Synchronous receive system reset recenters the receiver elastic buffer, and resets the
8B/10B decoder, comma detect, channel bonding, clock correction logic, and other
receiver registers. The PLL is unaffected.
TXRESET Synchronous transmit system reset recenters the transmission FIFO, and resets the
8B/10B encoder and other transmission registers. The PLL is unaffected.
POWERDOWN Shuts down the transceiver (both RX and TX sides).
In POWERDOWN mode, transmit output pins TXP/TXN are not driven, but biased by
the state of transmit termination supply VTTX. If VTTX is not powered, TXP/TXN
float to a high-impedance state. Receive input pins RXP/RXN respond similarly to the
state of receive termination supply VTRX.
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Chapter 2: Digital Design Considerations
Latency
±
0.5)
SERDES_10B = TRUE:
0.5 TXUSRCLK cycles (approx.)
Latency
±
0.5)
2 Byte Data Path:
1 RXUSRCLK2 cycle
1 RXUSRCLK cycle
Table 2-8
Description
4 Byte Data Path:
1.25 RXUSRCLK2 cycles
2.5 RXUSRCLK cycles
and Table 2-9.
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004