Reset And Initialization - Xilinx Virtex UltraScale+ FPGAs User Manual

Table 10: LCPLL Attributes (cont'd)
Attributes
SDM_CFG0[15:0]
Bit Name
SDM_WIDTHSEL
SDM_CFG1
SDM_CFG2
SDM_SEED_CFG0
SDM_SEED_CFG1
A_SDM_DATA_CFG0
A_SDM_DATA_CFG1

Reset and Initialization

The GTM transceiver must be initialized after device power-up and configuration before it can be
used. The GTM transmitter (TX) and receiver (RX) can be initialized independently and in parallel
as shown in the following figure. The GTM transceiver TX and RX initialization comprises three
steps:
1. Initializing the associated PLL driving TX/RX
2. Initializing the TX and RX datapaths (PMA + PCS)
The TX and RX in the GTM transceiver receive the clock through the LCPLL in the transceiver's
own Dual. In the power-on initialization sequence, the LCPLL used by the TX and RX must be
initialized first. The LCPLL used by the TX and RX is reset individually and its reset operation
independent from TX and RX resets. The TX and RX datapaths must be initialized only after the
associated LCPLL is locked.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Type
16-bit Reserved. Use the recommended value from the Wizard.
Address Description
[10:9] This attribute sets the denominator of the fractional part of
the feedback divider:
2'b00: 24 bits.
2'b01: 20 bits.
2'b10: 16 bits.
2'b11: Reserved.
16-bit Reserved. Use the recommended value from the Wizard.
16-bit Reserved. Use the recommended value from the Wizard.
16-bit Reserved. Use the recommended value from the Wizard.
16-bit Reserved. Use the recommended value from the Wizard.
16-bit Reserved. Use the recommended value from the Wizard.
16-bit Reserved. Use the recommended value from the Wizard.
Chapter 2: Shared Features
Description
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