Tx Initialization; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
X-Ref Target - Figure 3-7
For details about placement constraints and restrictions on clocking resources (MMCM,
BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources
User Guide.

TX Initialization

Functional Description

The GTX TX must be reset before it can be used. There are three ways to reset the GTX TX:
1.
2.
3.
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136
TXPLLLKDET/
RXPLLLKDET
TXOUTCLK
GTX
Transceiver
TXUSRCLK2
TXUSRCLK
TXDATA (8 or 10 bits)
TXUSRCLK2
GTX
TXUSRCLK
Transceiver
TXDATA (8 or 10 bits)
Note 1: F = 2 x F
TXUSRCLK2 TXUSRCLK
Figure 3-7: TXOUTCLK Driving More Than One GTX TX in 1-Byte Mode
Power up and configure the FPGA. Power-up reset is covered in this section.
Drive the GTXTXRESET port High to trigger a full asynchronous reset of the GTX TX.
Assert one or more of the individual reset signals on the block to reset a specific
subcomponent of the transmitter. These resets are covered in detail in the sections for
each subcomponent (refer to
resets).
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MMCM
CLKOUT0
RST
CLKOUT1
CLKIN
LOCKED
(1)
(1)
(1)
(1)
Table 3-9, page 140 for a list of the available transmitter
Virtex-6 FPGA GTX Transceivers User Guide
BUFG
BUFG
Design
in
FPGA
UG366_c3_22_061509
UG366 (v2.5) January 17, 2011