Transmitter Buffer; Crc; Reset/Power Down - Xilinx RocketIO User Manual

CRC

recognizes the "P" channel bonding character, and remembers its location in the buffer. At
some point, one transceiver designated as the master instructs all the transceivers to align
to the channel bonding character "P" (or to some location relative to the channel bonding
character). After this operation, the words transmitted to the FPGA core are properly
aligned: RRRR, SSSS, TTTT, etc., as shown in the bottom-right portion of
ensure that the channels remain properly aligned following the channel bonding
operation, the master transceiver must also control the clock correction operations
described in the previous section for all channel-bonded transceivers.

Transmitter Buffer

The transmitter buffer's write pointer (TXUSRCLK) is frequency-locked to its read pointer
(REFCLK). Therefore, clock correction and channel bonding are not required. The purpose
of the transmitter's buffer is to accommodate a phase difference between TXUSRCLK and
REFCLK. A simple FIFO suffices for this purpose. A FIFO depth of four permits reliable
operation with simple detection of overflow or underflow, which might occur if the clocks
are not frequency-locked.
CRC
The RocketIO transceiver CRC logic supports the 32-bit invariant CRC calculation used by
Infiniband, FibreChannel, and Gigabit Ethernet.
On the transmitter side, the CRC logic recognizes where the CRC bytes should be inserted
and replaces four placeholder bytes at the tail of a data packet with the computed CRC. For
Gigabit Ethernet and FibreChannel, transmitter CRC can adjust certain trailing bytes to
generate the required running disparity at the end of the packet.
On the receiver side, the CRC logic verifies the received CRC value, supporting the same
standards as above.
The CRC logic also supports a user mode, with a simple data packet structure beginning
and ending with user-defined SOP and EOP characters.
There are limitations to the CRC support provided by the RocketIO transceiver core:
•
•

Reset/Power Down

The receiver and transmitter have their own synchronous reset inputs. The transmitter
reset recenters the transmission FIFO and resets all transmitter registers and the 8B/10B
encoder. The receiver reset recenters the receiver elastic buffer and resets all receiver
registers and the 8B/10B decoder. Neither reset signal has any effect on the PLLs.
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
It is for single-channel use only. Computation and byte-striping of CRC across
multiple bonded channels is not supported. For that usage, the CRC logic can be
implemented in the FPGA fabric.
The RocketIO transceiver does not compute the 16-bit variant CRC used for
Infiniband. Therefore, RocketIO CRC does not fulfill the Infiniband CRC requirement.
Infiniband CRC can be computed in the FPGA fabric.
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