Pll Settings For The Common Protocol; Reset And Initialization; Functional Description - Xilinx Virtex-6 FPGA User Manual

PLL Settings for the Common Protocol

Table 2-9
transceiver supports.
Table 2-9: PLL Divider Settings for Common Protocols
Line Rate REFCLK
Protocol
[Gb/s] [MHz]
10GBASE-KR 10.3125 156.25
CEI11 11.096 173.37
9.953 155.52
OC-192 9.953 311.03
9.953 622.06
2.488 155.52
OC-48 2.488 311.03
2.488 622.06
2.677 166.69
OTU1
2.677 666.75
10.709 167.33
OTU2
10.709 669.31
10.7546 168.05
OTU3
10.7546 672.19
11.18 174.69
OTU4
11.18 698.75
XFP 9.953 155.52
Notes:
1. The settings for the TX_FABRIC_WIDTH and RX_FABRIC_WIDTH listed in this table are examples. The settings depend on the
external data width that the user selects for the fabric logic.

Reset and Initialization

Functional Description

The different ways to reset the GTH Quad are:
1.
2.
3.
All these methods are described in this section.
These items must be considered to initialize the GTH Quad properly:
•
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
shows example PLL divider settings for several standard protocols that the GTH
PLL Feedback
Divider PLL Freq TXRATE
PLL_CFG0[5:0] [GHz] RXRATE
(N – 1)
32 5.15625
2'b00
31 5.54784
2'b00
31 4.9765
2'b00
15 4.9765
2'b00
7 4.9765
2'b00
31 4.976
2'b10
15 4.976
2'b10
7 4.976
2'b10
31 5.334
2'b10
7 5.334
2'b10
31 5.35456
2'b00
7 5.35504
2'b00
31 5.3773
2'b00
7 5.3773
2'b00
31 5.590
2'b00
7 5.590
2'b00
31 4.9765
2'b00
Power-up and configure the FPGA.
Apply a reset sequence to the GTHRESET and GTHINIT ports.
Reset the PCS logic using the power-down ports.
DCLK must always be provided to the GTHE1_QUAD primitive even if the DRP or
management interface is not used.
Note:
DCLK must be sourced from a free-running clock. It cannot be sourced from
TSTREFCLKOUT or TSTREFCLKFAB of the GTH Quad.
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Quad
PLLPCSCLKDIV PCS SAMPLE
(N – 1) Clock RATE
[MHz]
32 156.25
3'b000
7 693.75
3'b000
7 622.06
3'b000
7 622.06
3'b000
7 622.06
3'b000
7 622.06
3'b010
7 622.06
3'b010
7 622.06
3'b010
7 666.75
3'b010
7 666.75
3'b010
7 669.31
3'b000
7 669.31
3'b000
7 672.16
3'b000
7 672.16
3'b000
7 698.75
3'b000
7 698.75
3'b000
7 622.07
3'b000
Reset and Initialization
Lane TX_FABRIC_WIDTH
TXUSERCLK
PCS RX_FABRIC_WIDTH
RXUSERCLK
Clock (Note 1)
156.25 156.25
3'b111
693.75 173.44
3'b010
622.06 155.52
3'b010
622.06 155.52
3'b010
622.06 155.52
3'b010
155.5 155.5
3'b000
155.5 155.5
3'b000
155.5 155.5
3'b000
166.69 166.69
3'b000
166.69 166.69
3'b000
669.31 167.33
3'b010
669.31 167.33
3'b010
672.16 168.04
3'b010
672.16 168.04
3'b010
698.75 174.69
3'b010
698.75 174.69
3'b010
622.07 155.52
3'b010
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