Tx Receiver Detect Support For Pci Express Designs; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

TX Receiver Detect Support for PCI Express Designs

Functional Description

The PCI Express specification includes a feature that allows the transmitter on a given link
to detect if a receiver is present. The decision if a receiver is present is based on the rise time
of TXP/TXN.
transceiver must be in the P1 power-down state to perform receiver detection. Also
receiver detection requires a 75 to 200 nF external coupling capacitor between the
transmitter and receiver, and the receiver must be terminated to GND. The detection
sequence starts with the assertion of TXDETECTRX. In response, the Receiver Detect logic
drives TXN and TXP to V
interval, the levels of TXN and TXP are compared with a threshold voltage. At the end of
the sequence, RXSTATUS and PHYSTATUS reflect the results of the receiver detection.
X-Ref Target - Figure 3-32

Ports and Attributes

Table 3-33
Table 3-33: TX Receiver Detect Support Ports
Port
PHYSTATUS
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Figure 3-32 shows the circuit model used for receive detection. The GTX
– V
DD
V
DD
R : 40Ω - 60Ω
TERMT
TXP
TXDETECTRX
GTX Transceiver
Components
Figure 3-32: Receiver Detection Circuit Model
defines the TX receiver detect support ports.
Dir Clock Domain
Out RXUSRCLK2/
Async
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TX Receiver Detect Support for PCI Express Designs
/2 and then releases them. After a programmable
SWING
C : 75 nF - 200 nF
AC
C : < 3 nF
CH
Channel
Components
Description
This signal is asserted High to indicate completion of
several PHY functions, including power management
state transitions and receiver detection. When this
signal transitions during entry and exit from P2 and
RXUSRCLK2 is not running, the signaling is
asynchronous.
R : 40Ω - 60Ω
TERMR
V
TERMR
Far-End Receiver
Components
UG366_c3_20_051509
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