Pci Express Receive Detect Support; Overview; Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 6: GTP Transmitter (TX)

PCI Express Receive Detect Support

Overview

The GTP transceiver supports receiver detect functionality as defined by the PHY Interface
for PCI Express (PIPE) Specification. This function drives the TX link to one state followed by
a second state and then measures the time required for the link voltage to change. The PIPE
specification provides details about the receiver detection mechanism.

Ports and Attributes

Table 6-19
Table 6-19: PCI Express Receive Detect Support Ports
Port
PHYSTATUS0
PHYSTATUS1
RXSTATUS0[2:0]
RXSTATUS1[2:0]
116
shows the ports associated with this function.
Dir Domain
This signal is asserted High to indicate completion of several PHY
functions, including power management state transitions and
Out Async receiver detection. When this signal transitions during entry and exit
from P2 and RXUSRCLK2 is not running, the signaling is
asynchronous.
The decoding of RXSTATUS[2:0] depends on the setting of
RX_STATUS_FMT.
When RX_STATUS_FMT = PCIE:
000: Receiver not present (when in receiver detection
sequence)/Received data OK (during normal operation)
001: Reserved
010: Reserved
011: Receiver present (when in receiver detection sequence)
100: 8B/10B decode error
Out RXUSRCLK2
101: Elastic Buffer Overflow. Different than defined in the PIPE
specification.
110: Elastic Buffer Underflow. Different than defined in the PIPE
specification.
111: Receive Disparity Error
When RX_STATUS_FMT = SATA:
RXSTATUS[0]: TXCOMSTART operation complete
RXSTATUS[1]: COMWAKE signal received
RXSTATUS[2]: COMRESET/COMINIT signal received
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Description
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
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