Timing Parameters; Input Setup/Hold Times Relative To Clock; Clock To Output Delays; Clock Pulse Width - Xilinx Virtex-4 RocketIO User Manual

Appendix A: RocketIO Transceiver Timing Model

Timing Parameters

Parameter designations are constructed to reflect the functions they perform, as well as the
I/O signals to which they are synchronous. The following subsections explain the meaning
of each of the basic timing parameter designations used in the tables.

Input Setup/Hold Times Relative to Clock

Basic Format:

Clock to Output Delays

Basic Format:

Clock Pulse Width

ParameterName Format:
Pulse Width (Examples):
274
ParameterName_SIGNAL
where
ParameterName = T with subscript string defining the timing
relationship
SIGNAL = name of RocketIO signal synchronous to the clock
ParameterName Format:
T = Setup time before clock edge
GxCK
T = Hold time after clock edge
GCKx
where
x = C (Control inputs)
D (Data inputs)
Setup/Hold Time (Examples):
T _RRST/T _PLB Setup/hold times of RX Reset input
GCCK GCKC
relative to rising edge of RXUSRCLK2
T _TDAT/T _TDAT Setup/hold times of TX Data inputs
GDCK GCKD
relative to rising edge of TXUSRCLK2
ParameterName_SIGNAL
where
ParameterName = T with subscript string defining the timing
relationship
SIGNAL = name of RocketIO signal synchronous to the clock
ParameterName Format:
T = Delay time from clock edge to output
GCKo
Output Delay Time (Examples):
T _CHBO Rising edge of RXUSRCLK to Channel Bond outputs
GCKO
T _RDAT Rising edge of RXUSRCLK2 to RX Data outputs
GCKO
T _TBERR Rising edge of TXUSRCLK2 to TX Buffer Err output
GCKO
T = Minimum pulse width, High state
xPWH
T = Minimum pulse width, Low state
xPWL
where
x = REF (REFCLK)
TX (TXUSRCLK)
TX2 (TXUSRCLK2)
RX (RXUSRCLK)
RX2 (RXUSRCLK2)
T Minimum pulse width, TX2 clock, Low state
TX2PWL
T Minimum pulse width, Reference clock, High state
REFPWH
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UG076 (v4.1) November 2, 2008
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