Tx Polarity Control; Functional Description; Ports And Attributes; Using Tx Polarity Control - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter

TX Polarity Control

Functional Description

The GTH transceiver includes a TX polarity control function to invert outgoing data from
the PCS before serialization and transmission.

Ports and Attributes

There are no TX polarity control ports.
Table 3-13
Table 3-13: TX Polarity Control Attributes
Attribute
PCS_MISC_CFG_0_LANE0
PCS_MISC_CFG_0_LANE1
PCS_MISC_CFG_0_LANE2
PCS_MISC_CFG_0_LANE3

Using TX Polarity Control

If the TXP/TXN differential traces are swapped on a board, use either the DRP or the
management interface to set PCS_MISC_CFG_0_LANE<n>[11] register to 1'b1. The
register is located in:
•
•
96
defines the TX polarity control attributes.
Type
16-bit Hex This attribute sets the polarity and PRBS configuration.
[15:12]: Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
[11]: Invert TX polarity
[10]: RX polarity override enable
[9]: RX polarity override value
[8]: Reset the PRBS error counter when read
[7]: Revert bit order of parallel data to serializer/deserializer TX
[6]: Revert bit order of parallel data from serializer/deserializer RX
[5:0]: Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
DRP Address
• PCS_MISC_CFG_0_LANE0: 0x5001
• PCS_MISC_CFG_0_LANE1: 0x5101
• PCS_MISC_CFG_0_LANE2: 0x5201
• PCS_MISC_CFG_0_LANE3: 0x5301
Management Interface Address: 0x8001 with MMD Address 0x03
• Use the Lane Address setting to specify which GTH lane to access
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010