Tx Fabric Clock Output Control; Functional Description - Xilinx Virtex-6 FPGA User Manual

TX Fabric Clock Output Control

Functional Description

The TX Fabric Clock Output Control block has two main components: serial clock divider
control and parallel clock divider and selector control. The clock divider and selector
details are illustrated in
X-Ref Target - Figure 3-28
GTXE1 (GTX Transceiver Primitive)
TXP/N
PLL
MGT
REFCLK
0/1
Notes relevant to
1.
2.
3.
4.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Figure
TX PMA
TXDATA
Phase
PISO
Interp
/D /4 or
/2
{1,2,4} /5
TX
RX
PLL
/2
REFCLK Sel
REFCLK Distribution
IBUFDS_GTXE1
O
/2
REFCLK_CTRL
Figure 3-28: TX Serial and Parallel Clock Divider Detail
Figure 3-28:
TXOUTCLKPCS and MGTREFCLKFAB[0] are redundant outputs. Use TXOUTCLK
for new designs.
The REFCLK_CTRL option is controlled automatically by software and is not user
selectable. The user can only route one of IBUFDS_GTXE1's O or ODIV2 outputs to the
fabric.
IBUFDS_GTXE1 is a redundant output for additional clocking scheme flexibility.
The RX PLL resides in the RX portion of the same GTX transceiver. It can be used in
place of the TX PLL for low-power operation.
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TX Fabric Clock Output Control
3-28.
TX PCS
TX Over-
sampler
TXOUTCLKPCS
TXOUTCLKPMA_DIV1
TXOUTCLKPMA_DIV2
TXPLLREFCLK_DIV1
TXPLLREFCLK_DIV2
TXOUTCLK_CTRL (Attribute)
O
0
ODIV2
1
TXDATA From
Upstream
PCS Blocks
TXOUTCLKPCS
000
001
TXOUTCLK
010
011
100
MGTREFCLKFAB[0]
IBUFDS_GTXE1
Output to Fabric
UG366_c3_18_051809
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