Register Definition; Masterbias[1:0]; Vcodac[5:0]; Txdivratio[9:0] - Xilinx RocketIO X User Manual

Register Definition

Table C-2: PMA Attribute Memory Map
Address Register Name
0x0B RXMODE1
0x0C RXFEICONTROL0
0x0D RXFEICONTROL1
0x0E <reserved>
0x0F POWERCONTROL
0x10-0x3F <reserved>
Register Definition
This section defines the individual PMA attribute vectors, as presented in

MASTERBIAS[1:0]

MASTERBIAS[1:0] selects the reference voltage used to generate bias currents throughout
the Multi-Gigabit Transceiver (MGT). The default for all primitives is 00 (Bandgap). The
voltage selection is as follows:

Table C-3: MASTERBIAS[1:0] Definition

VCODAC[5:0]

VCODAC[5:0] is a binary weighted current used to set the VCO center frequency in the
transmit or receive VCO, when TXVCODAC or RXVCODAC, respectively, are Low or
High. When in automatic mode (default), this value is unused.

TXDIVRATIO[9:0]

TXDIVRATIO[9:0] controls the divider ratios for TXCLK0, TXOUTCLK, and the PLL clock
multiplier ratio of the transmitter relative. The defaults for these are primitive dependent,
based on reference clock frequency and encoding.

Table C-4: TX Clock Multiplier Ratio Definition

RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
7 6
RXCPGAIN RXVSELCP[1:0]
RXFER[1:0]
TXDRVEN RXEN
MASTERBIAS[1:0]
00 Bandgap, Nominal Voltage (Default)
01
10
11 Voltage Divider, Bandgap Unused
TXDIVRATIO[3:0]
0000
0001
0010
0011
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5 4 3
RXFLCPI[1:0]
RXFER[9:2]
TXEN RXANAEN
Voltage Reference
Bandgap, Higher Current
Bandgap, Lower Current
Divider
÷ 4
÷ 4.125
÷ 5
Reserved
2 1
RXFLTCPT[4:0]
RXFEI[1:0] VSELAFE[1:0]
TXDIGEN TXANAEN
Table
R
0
BIASEN
C-2.
149