Tx Fabric Clock Output Control - Xilinx Virtex UltraScale+ FPGAs User Manual

Ports and Attributes
The following table defines the attributes required for TX pre-coder control.
Table 42: Pre-Coder Attributes
Attribute
CH[0/1]_TX_PCS_CFG0
Bit Name
TX_PRECODE_ENDIAN
TX_PRECODE_BYP_EN
IMPORTANT! In PAM4 mode, if pre-coder is enabled for the transmitter, the receiver pre-coder should
also be enabled for proper data recovery.

TX Fabric Clock Output Control

The TX Clock Divider Control block has two main components: serial clock divider control, and
parallel clock divider and selector control. The clock divider and selector details are illustrated in
the following figure.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Type
16-bit Reserved.
Address Description
[11] In PAM4 mode, this attribute controls pre-coder
transmitted endianness. In NRZ mode, the default
Wizard value must be used.
1'b0: Non-inverting.
1'b1: Inverting.
[10] In PAM4 mode, this attribute enables pre-coding. In
NRZ mode, the default Wizard value must be used.
1'b0: Enables pre-code.
1'b1: Disables pre-code.
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Chapter 3: Transmitter
Description
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