Setup/Hold Times Of Inputs Relative To Clock; Clock To Output Delays; Clock Pulse Width - Xilinx RocketIO User Manual

Timing Parameters

Setup/Hold Times of Inputs Relative to Clock

Basic Format:
ParameterName Format:
Setup/Hold Time (Examples):

Clock to Output Delays

Basic Format:
ParameterName Format:
Output Delay Time (Examples):

Clock Pulse Width

ParameterName Format:
Pulse Width (Examples):
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
ParameterName_SIGNAL
where
ParameterName = T with subscript string defining the timing relationship
SIGNAL = name of RocketIO signal synchronous to the clock
T = Setup time before clock edge
GxCK
T = Hold time after clock edge
GCKx
where
x = C (Control inputs)
D (Data inputs)
T _RRST/T
GCCK GCKC
T _TDAT/T
GDCK GCKD
ParameterName_SIGNAL
where
ParameterName = T with subscript string defining the timing relationship
SIGNAL = name of RocketIO signal synchronous to the clock
T = Delay time from clock edge to output
GCKx
where
x = CO (Control outputs)
DO (Data outputs)
ST (Status outputs)
T _CHBO
GCKCO
T _RDAT
GCKDO
T _TBERR
GCKST
T = Minimum pulse width, High state
xPWH
T = Minimum pulse width, Low state
xPWL
where
x = REF (REFCLK)
TX (TXUSRCLK)
TX2 (TXUSRCLK2)
RX (RXUSRCLK)
RX2 (RXUSRCLK2)
T Minimum pulse width, TX2 clock, Low state
TX2PWL
T Minimum pulse width, Reference clock, High state
REFPWH
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_PLB Setup/hold times of RX Reset input
relative to rising edge of RXUSRCLK2
_TDAT Setup/hold times of TX Data inputs
relative to rising edge of TXUSRCLK2
Rising edge of RXUSRCLK to Channel Bond outputs
Rising edge of RXUSRCLK2 to RX Data outputs
Rising edge of TXUSRCLK2 to TX Buffer Err output
R
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