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6.3.2.114 DDC I2C Data Count Register (DDC_COUNT2)
The DDC I2C data count register is shown in
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-145. DDC I2C Data Count Register (DDC_COUNT2) Field Descriptions
Bit
Field
31-8
Reserved
7-0
DDC_COUNT
6.3.2.115 DDC I2C Status Register (DDC_STATUS)
The DDC I2C Status Register (DDC_STATUS) is shown in
31
15
7
6
Reserved
BUS_LOW
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-146. DDC I2C Status Register (DDC_STATUS) Field Descriptions
Bit
Field
31-7
Reserved
6
BUS_LOW
5
NO_ACK
4
IN_PROG
3
FIFO_FULL
2
FIFO_EMP
1
FRD_USE
0
FWT_USE
SPRUGX9 – 15 April 2011
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Preliminary
Figure 6-136. DDC I2C Data Count Register (DDC_COUNT2)
Reserved
R-0h
Description
Reserved
The total number of bytes to be read from the slave or written to the slave before a Stop bit is sent on the
DDC bus. For example, if the HDCP KSV FIFO length is 635 bytes (127 devices x 5 bytes/KSV), the
DDC_COUNT must be 27Bh.
Figure 6-137. DDC I2C Status Register (DDC_STATUS)
5
4
NO_ACK
IN_PROG
R-0h
R-0h
Description
Reserved
1 = I2C transaction did not start because I2C bus is pulled LOW by an external device
1 = HDMI transmitter did not receive an ACK from slave device during address or data write
1 = DDC operation in progress
1 = DDC FIFO full
1 = DDC FIFO empty
1 = DDC FIFO read in use
1 = DDC FIFO write in use
© 2011, Texas Instruments Incorporated
Figure 6-136
and described in
Figure 6-137
Reserved
R-0h
Reserved
R-0h
3
2
FIFO_FULL
FIFO_EMP
R-0h
R-1h
High-Definition Multimedia Interface (HDMI)
Registers
Table
6-145.
8
7
DDC_COUNT2
R/W-0h
and described in
Table
6-146.
8
1
0
FRD_USE
FWT_USE
R-0h
R-0h
0
16
803
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