Ddc I2C Command Register (Ddc_Cmd); Ddc I2C Data Register (Ddc_Data); Ddc I2C Command Register (Ddc_Cmd) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

6.3.2.116 DDC I2C Command Register (DDC_CMD)

The DDC I2C command register is shown in
31
15
7 6
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-147. DDC I2C Command Register (DDC_CMD) Field Descriptions
Bit Field
31-6 Reserved
5 DDC_FLT_EN
4 SDA_DEL_EN
3-0 DDC_CMD
0b1111 Abort transaction
0b1001 Clear FIFO
0b1010 Clock SCL
0b0000 Current address read with no ACK on last byte
0b0010 Sequential read with no ACK on last byte
0b0100 Enhanced DDC read with no ACK on last byte
0b0110 Sequential write ignoring ACK on last byte
0b0111 Sequential write requiring ACK on last byte

6.3.2.117 DDC I2C Data Register (DDC_DATA)

The DDC I2C data register is shown in
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
804
High-Definition Multimedia Interface (HDMI)
Preliminary
Figure 6-138. DDC I2C Command Register (DDC_CMD)
5 4
DDC_FLT_EN SDA_DEL_EN
R/W R/W
Value Description
0 Reserved
Enable the DCC delay. A DDC delay is inserted into the SDA line to create a 300 ns delay for the
falling edge of the DDC SDA signal to avoid an erroneous I2C START condition. The real start
condition must have a setup time of 600 ns so that this delay of 300 ns does not remove the real
START condition. Filtering is done using a ring oscillator.
0 Enabled
1 Disabled
Enable 3 ns glitch filtering on the DDC clock and data line. Filtering is done using a ring oscillator.
0 Enabled
1 Disabled
0 DDC command
Writing to this register immediately initiates the I2C transaction on the DDC bus. Note: The clear
FIFO command resets the FIFO read and write pointers to zero. Data formerly loaded into the FIFO
cannot be re-read after a clear FIFO, as the FIFO will be empty. Other command codes are
reserved and may cause the DDC bus to hang if used. The clock SCL command resets any I2C
devices on the DDC lines. This should be initiated once before initiating the DDC commands.
Figure 6-139
Figure 6-139. DDC I2C Data Register (DDC_DATA)
Reserved
R-0h
© 2011, Texas Instruments Incorporated
Figure 6-138 and described in
Reserved
R-0h
Reserved
R-0h
3
and described in Table
www.ti.com
Table 6-147.
8
0
DDC_CMD
R/W
6-148.
8 7
DDC_DATA
R/W-0h
SPRUGX9 – 15 April 2011
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