Hitachi SH7750 Hardware Manual page 500

Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w
CKIO
A25–A0
RD/
*
(read)
D15–D0
(read)
(write)
D15–D0
(write)
DACKn
(DA)
Notes: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
* SH7750S, SH7750R only
Figure 13.51 Wait Timing for PCMCIA Memory Card Interface
Rev. 6.0, 07/02, page 450 of 986