Hitachi SH7750 Hardware Manual page 13

Section
14.2.1 DMA Source Address
Registers 0–3 (SAR0–SAR3)
14.2.2 DMA Destination
Address Registers 0–3
(DAR0–DAR3)
14.2.3 DMA Transfer Count
Registers 0–3 (DMATCR0–
DMATCR3)
14.2.4 DMA Channel Control
Registers 0–3 (CHCR0–
CHCR3)
14.2.5 DMA Operation
Register (DMAOR)
14.3.2 DMA Transfer
Requests
14.3.4 Types of DMA
Transfer
14.3.5 Number of Bus Cycle
States and DREQ Pin
Sampling Timing
14.5 On-Demand Data
Transfer Mode (DDT Mode)
14.5.2 Pins in DDT Mode
14.5.3 Transfer Request
Acceptance on Each Channel 553
14.5.4 Notes on Use of DDT
Module
Page Item
496
497
498
499
502, 503 Bits 19 to 16
503 Bits 15, 14 and Bits 13, 12
505 Bits 6 to 4
508 Bit 4
513 • External Request
Acceptance Conditions
526 Table 14.9 External Request
Transfer Sources and
Destinations in DDT Mode
525 (a) Normal DMA Mode
533 to Figure 14.15 to 14.17
535
545
BAVL: Data bus D63–D0
547
release signal
551, 552 Figures 14.26, 14.27
Figure 14.28
554 Figure 14.29
554, 555 Figure 14.30, 14.31
572 c. of 3. Handshake protocol
using the data bus (valid on
channel 0 only)
573 b. of 8. Data transfer end
request
573 12. Confirming DMA transfer
requests and number of
transfers executed
Description
Description amended
Description amended
Description amended
Description of DDT
mode added
Initial value changed
Description amended
Description added
Description amended
Description added
Usable DMAC channels
changed
Description amendment
Figure description
added
Description
amendments
Description added
Title amended
Newly added
Amended
Errors corrected
Description amended
Added
Description amended
Rev. 6.0, 07/02, page xiii of I