Store Queues; Sq Configuration; Sq Writes; Transfer To External Memory - Hitachi SH7750 Hardware Manual

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Store Queues

The SH7750 Series supports two 32-byte store queues (SQs) to perform high-speed writes to

external memory.

In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down

modes, in which SQ functions are stopped, can be used. The queue address control registers

(QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, Power-

Down Modes, for the procedure for stopping SQ functions.

There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store

queues can be set independently.

A write to the SQs can be performed using a store instruction (MOV) on P4 area H'E000 0000 to

H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits

is as follows:

LW specification

Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).

Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from

the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is

always at a 32-byte boundary. While the contents of one SQ are being transferred to external

Rev. 6.0, 07/02, page 122 of 986

Store queue specification

Used for external memory transfer/access right

0: SQ0 specification

Specifies longword position in SQ0/SQ1

1: SQ1 specification

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