Hitachi SH7750 Hardware Manual page 66

Table 1.2 Pin Functions (cont)
Pin
No. No. Pin Name
87 V9 VDDQ
88 U9 VSSQ
89 Y9 A9
90 W10 A8
91 Y10 A7
92 Y11 CKIO
93 V10 VDDQ
94 U10 VSSQ
95 W11 CKIO2
96 Y12 A6
97 W12 A5
98 Y13 A4
99 V11 VDDQ
100 U11 VSSQ
101 W13 A3
102 Y14 A2
103 V12 DRAK1
104 U13 DRAK0
105 V13 VDDQ
106 U12 VSSQ
CS3
107 W14
CS2
108 Y15
109 V14 VDD
110 U14 VSS
RAS
111 W15
RD/CASS/
112 Y16
FRAME
113 V15 VDDQ
114 U15 VSSQ
Rev. 6.0, 07/02, page 16 of 986
I/O Function
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
O Clock output
Power IO VDD (3.3 V)
Power IO GND (0 V)
1
CKIO *
O
O Address
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O DMAC1
request
acknowledge
O DMAC0
request
acknowledge
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Chip select 3
O Chip select 2
Power Internal VDD
Power Internal GND
(0 V)
RAS
O
O Read/CAS/
FRAME
Power IO VDD (3.3 V)
Power IO GND (0 V)
Reset SRAM DRAM
CS3
(CS3)
CS2
(CS2)
RAS
OE
Memory Interface
SDRAM PCMCIA MPX
CKIO
CKIO
CS3 CS3
CS2 CS2
RAS
CAS OE FRAME