Register Configuration; Table 4.3 Features Of Store Queues; Table 4.4 Cache Control Registers - Hitachi SH7750 Hardware Manual

Table 4.3 Features of Store Queues
Item
Capacity
Addresses
Write
Write-back
Access right
4.1.2

Register Configuration

Table 4.4 shows the cache control registers.
Table 4.4 Cache Control Registers
Name
Cache control
register
Queue address
control register 0
Queue address
control register 1
Notes: *1 The initial value is the value after a power-on or manual reset.
*2 This is the address when using the virtual/physical address space P4 area. The area 7
address is the address used when making an access from physical address space area
7 using the TLB.
Rev. 6.0, 07/02, page 96 of 986
Store Queues
2 × 32 bytes
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
MMU off: according to MMUCR.SQMD
MMU on: according to individual page PR
Abbreviation R/W
CCR R/W
QACR0 R/W
QACR1 R/W
Initial P4
1
Value * Address *
H'0000 0000 H'FF00 001C
Undefined H'FF00 0038
Undefined H'FF00 003C
Area 7
2 2
Address *
H'1F00 001C
H'1F00 0038
H'1F00 003C
Access
Size
32
32
32