Data Format - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Data Format

Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is

carried out on each frame, and if an error is detected an error signal is sent back to the transmitting

side to request retransmission of the data. If an error signal is detected during transmission, the

same data is retransmitted.

When there is no parity error

When a parity error occurs

D0–D7: Data bits

Error signal

The operation sequence is as follows.

1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

2. The transmitting station starts transmission of one frame of data. The data frame starts with a

start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

3. With the smart card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

4. The receiving station carries out a parity check.

If there is no parity error and the data is received normally, the receiving station waits for

reception of the next data.

Rev. 6.0, 07/02, page 712 of 986

Transmitting station output

Figure 17.3 Smart Card Interface Data Format

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