Figure 13.24 Dram Cas-Before-Ras Refresh Cycle Timing (Tras = 0, Trc = 1) - Hitachi SH7750 Hardware Manual

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Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)

• Self-Refresh

The self-refreshing supported by the SH7750 Series is shown in figure 13.25.

After the self-refresh is cleared, the refresh controller immediately generates a refresh request.

The RAS precharge time immediately after the end of the self-refreshing can be set by bits

TRC2–TRC0 in MCR.

DRAMs include low-power products (L versions) with a long refresh cycle time (for example,

the HM51W4160AL L version has a refresh cycle of 1024 cycles/128 ms compared with 1024

cycles/16 ms for the normal version). With these DRAMs, however, the same refresh cycle as

for the normal version is requested only in the case of refreshing immediately following self-

refreshing. To ensure efficient DRAM refreshing, therefore, processing is needed to generate

an overflow interrupt and restore the refresh cycle to the proper value, after the necessary

CAS-before-RAS refreshing has been performed following self-refreshing of an L-version

DRAM, using the OVF, OVIE, and LMTS bits in RTCSR and the refresh controller's refresh

count register (RFCR). The necessary procedure is as follows.

Rev. 6.0, 07/02, page 410 of 986

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