Cpg Pin Configuration; Cpg Register Configuration; Table 10.1 Cpg Pins; Table 10.2 Cpg Register - Hitachi SH7750 Hardware Manual

10.2.2

CPG Pin Configuration

Table 10.1 shows the CPG pins and their functions.

Table 10.1 CPG Pins

Pin Name
Mode control pins
Crystal I/O pins
(clock input pins)
Clock output pin
CKIO enable pin
Note: * Set to 1 in a power-on reset.
For details of synchronous DRAM self-refreshing, see section 13.3.5, Synchronous DRAM
Interface.
10.2.3

CPG Register Configuration

Table 10.2 shows the CPG register configuration.

Table 10.2 CPG Register

Name
Frequency control
register
Note: * Depends on the clock operating mode set by pins MD2–MD0.
Rev. 6.0, 07/02, page 252 of 986
Abbreviation I/O
MD0 Input
MD1
MD2
XTAL Output
EXTAL Input
MD8 Input
CKIO Output
CKE Output
Abbreviation R/W
FRQCR R/W
Function
Set clock operating mode
Connects crystal resonator
Connects crystal resonator, or used as
external clock input pin
Selects use/non-use of crystal resonator
When MD8 = 0, external clock is input from
EXTAL
When MD8 = 1, crystal resonator is
connected directly to EXTAL and XTAL
Used as external clock output pin
Level can also be fixed
0 when CKIO output clock is unstable and in
case of synchronous DRAM self-refreshing*
Initial Value P4 Address
Undefined* H'FFC00000 H'1FC00000
Area 7 Access
Address Size
16