Break Data Mask Register B (Bdmrb) - Hitachi SH7750 Hardware Manual

Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be
used in the channel B break conditions.

20.2.10 Break Data Mask Register B (BDMRB)

Bit:
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
Initial value:
R/W:
Bit:
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
Initial value:
R/W:
Bit:
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: *: Undefined
Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which
bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on
reset or manual reset.
Rev. 6.0, 07/02, page 782 of 986
31 30
* *
R/W R/W
23 22
* *
R/W R/W
15 14
* *
R/W R/W
7 6
BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0
* *
R/W R/W
29 28 27
* *
R/W R/W R/W
21 20 19
* *
R/W R/W R/W
13 12 11
* *
R/W R/W R/W
5 4
* *
R/W R/W R/W
26 25
* * *
R/W R/W
18 17
* * *
R/W R/W
10 9
* * *
R/W R/W
3 2 1
* * *
R/W R/W
24
*
R/W
16
*
R/W
8
*
R/W
0
*
R/W