Hitachi SH7750 Hardware Manual page 578

In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins,
at the earliest, five CKIO cycles after the first sampling operation. The second sampling
operation begins from the cycle in which the first DMAC transfer read cycle ends. If DREQ is
not detected at this time, sampling is executed in every subsequent cycle.
For details of the timing for various kinds of memory access, see section 13, Bus State
Controller (BSC).
Figure 14.18 shows the case of cycle steal mode, single address mode, and level detection. In
this case, too, transfer is started, at the earliest, four CKIO cycles after the first DREQ
sampling operation. The second sampling operation is performed one cycle after the start of
the first DMAC transfer bus cycle.
Figure 14.19 shows the case of cycle steal mode, single address mode, and edge detection. In
this case, transfer is started, at the earliest, five CKIO cycles after the first DREQ sampling
operation. The second sampling begins one cycle after the first assertion of DRAK.
In single address mode, the DACK signal is output every DMAC transfer cycle.
2. Burst Mode, Dual Address Mode, Level Detection
DREQ sampling timing in burst mode using dual address mode and level detection is virtually
the same as for cycle steal mode.
For example, in figure 14.14, DMAC transfer begins, at the earliest, four CKIO cycles after the
first sampling operation. The second sampling operation is performed one cycle after the start
of the first DMAC transfer write cycle.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
3. Burst Mode, Single Address Mode, Level Detection
DREQ sampling timing in burst mode using single address mode and level detection is shown
in figure 14.20.
In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles
after the first sampling operation, and the second sampling operation begins one cycle after the
start of the first DMAC transfer bus cycle.
In single address mode, the DACK signal is output every DMAC transfer cycle.
In figure 14.22, with a 32-byte data size, 64-bit bus width, and SDRAM: row hit write, DMAC
transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second
sampling operation begins one cycle after DACK is asserted for the first DMAC transfer.
4. Burst Mode, Dual Address Mode, Edge Detection
In burst mode using dual address mode and edge detection, DREQ sampling is performed in
the first cycle only.
Rev. 6.0, 07/02, page 528 of 986