Hitachi SH7750 Hardware Manual page 52

Table 1.1 SH7750 Series Features (cont)
Item
CPU
Rev. 6.0, 07/02, page 2 of 986
Features
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Original Hitachi SH architecture
•
32-bit internal data bus
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General register file:
 Sixteen 32-bit general registers (and eight 32-bit shadow registers)
 Seven 32-bit control registers
 Four 32-bit system registers
•
RISC-type instruction set (upward-compatible with SH Series)
 Fixed 16-bit instruction length for improved code efficiency
 Load-store architecture
 Delayed branch instructions
 Conditional execution
 C-based instruction set
•
Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
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Instruction execution time: Maximum 2 instructions/cycle
•
Virtual address space: 4 Gbytes (448-Mbyte external memory space)
•
Space identifier ASIDs: 8 bits, 256 virtual address spaces
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On-chip multiplier
•
Five-stage pipeline