Block Diagram; Figure 1.1 Block Diagram Of Sh7750 Series Functions - Hitachi SH7750 Hardware Manual

1.2

Block Diagram

Figure 1.1 shows an internal block diagram of the SH7750 Series.
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)

Figure 1.1 Block Diagram of SH7750 Series Functions

CPU
Lower 32-bit data
I cache ITLB
CPG
INTC
SCI
(SCIF)
RTC
TMU
26-bit
address
UBC
Lower 32-bit data
Cache and
UTLB
TLB
controller
BSC
External
bus interface
64-bit
data
UTLB: Unified TLB (translation lookaside buffer)
RTC: Realtime clock
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
TMU: Timer unit
UBC: User break controller
Rev. 6.0, 07/02, page 9 of 986
FPU
O cache
DMAC