Hitachi SH7750 Hardware Manual page 802

NMI
–
4
(Interrupt request)
TMU
(Interrupt request)
RTC
(Interrupt request)
SCI
(Interrupt request)
SCIF
(Interrupt request)
WDT
(Interrupt request)
REF
(Interrupt request)
DMAC
(Interrupt request)
H-UDI
(Interrupt request)
GPIO
TMU: Timer unit
RTC: Realtime clock unit
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
WDT: Watchdog timer
REF: Memory refresh controller section of the bus state controller
DMAC: Direct memory access controller
H-UDI: Hitachi user debug interface
GPIO: I/O port
ICR: Interrupt control register
IPRA–IPRD: Interrupt priority registers A–D
INTPRI00: Interrupt priority level setting register 00
SR: Status register
Notes: *1 IPRD is provided only in the SH7750S and SH7750R.
*2 INTPRI00 is provided only in the SH7750R.
Rev. 6.0, 07/02, page 752 of 986
Input control
4
ICR
*1
Figure 19.1 Block Diagram of INTC
Com-
Priority
parator
identifier
IPR
*1
IPRA–IPRD
*2
INTPRI00
Bus interface
*2
Interrupt
request
SR
I3 I2 I1 I0
CPU
INTC