Table 13.7 (2)
64-Bit External Device/Big-Endian Access and Data Alignment
Operation
Access
Size
Address No.
Byte
8n
1
8n+1
1
8n+2
1
8n+3
1
8n+4
1
8n+5
1
8n+6
1
8n+7
1
Word
8n
1
8n+2
1
8n+4
1
8n+6
1
Long-
8n
1
word
8n+4
1
Quad-
8n
1
word
WE7,
WE7
WE6,
WE6
WE5,
WE5
WE7
WE7
WE6
WE6
WE5
WE5
CAS7,
CAS7
CAS7
CAS7
CAS6,
CAS6
CAS6
CAS6
CAS5,
CAS5
CAS5
CAS5
DQM7
DQM6
DQM5
Asserted
Asserted
Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted
Strobe Signals
WE4
WE4,
WE3,
WE3
WE2,
WE2
WE4
WE4
WE3
WE3
WE2
WE2
CAS4
CAS4
CAS4
CAS4,
CAS3,
CAS3
CAS3
CAS3
CAS2
CAS2,
CAS2
CAS2
DQM4
DQM3
DQM2
Asserted
Asserted
Asserted
Asserted Asserted
Asserted Asserted Asserted Asserted
Rev. 6.0, 07/02, page 373 of 986
WE1,
WE1
WE0,
WE0
WE1
WE1
WE0
WE0
CAS1,
CAS1
CAS1
CAS1
CAS0
CAS0,
CAS0
CAS0
DQM1
DQM0
Asserted
Asserted
Asserted Asserted