Figure 22.29 Synchronous Dram Auto-Precharge Write Bus Cycle: Burst (Rcd[1:0] = 01, Tpc[2:0] = 001, Trwl[2:0] = 010) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

Hide thumbs Also See for SH7750:

Table of Contents

Precharge-sel

(SA: IO → memory)

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst

(RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)

Rev. 6.0, 07/02, page 891 of 986

Chapters

Table of Contents

Sh7750r Sh7750s