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SuperH™ (SH) 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Programming Manual ADE-602-156A Rev. 2.0 03/04/99 Hitachi, Ltd.
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
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Preface The SH-4 (SH7750) has been developed as the top-end model in the SuperH™ RISC engine family, featuring a 128-bit graphic engine for multimedia applications and 360 MIPS performance. The SH7750 CPU has a RISC type instruction set, and features upward-compatibility at the object code level with SH-1, SH-2, SH-3, and SH-3E microcomputers.
Page 7: Table Of Contents

Contents Section 1 Overview ......................SH7750 Features....................... Block Diagram........................Section 2 Programming Model ..................Data Formats........................Register Configuration...................... 10 2.2.1 Privileged Mode and Banks................. 10 2.2.2 General Registers....................13 2.2.3 Floating-Point Registers ..................15 2.2.4 Control Registers ....................17 2.2.5 System Registers....................
Page 8: Table Of Contents

3.5.2 MMU Software Management ................45 3.5.3 MMU Instruction (LDTLB) ................45 3.5.4 Hardware ITLB Miss Handling ................46 3.5.5 Avoiding Synonym Problems................47 MMU Exceptions......................48 3.6.1 Instruction TLB Multiple Hit Exception.............. 48 3.6.2 Instruction TLB Miss Exception................49 3.6.3 Instruction TLB Protection Violation Exception ..........
Page 9: Table Of Contents

4.5.4 OC Data Array..................... 78 Store Queues........................79 4.6.1 SQ Configuration....................79 4.6.2 SQ Writes ......................79 4.6.3 Transfer to External Memory ................79 4.6.4 SQ Protection....................... 81 Section 5 Exceptions ......................83 Overview .......................... 83 5.1.1 Features........................ 83 5.1.2 Register Configuration..................
Page 10: Table Of Contents

6.6.2 Pair Single-Precision Data Transfer ..............128 Section 7 Instruction Set ....................129 Execution Environment ....................129 Addressing Modes ......................131 Instruction Set........................135 Section 8 Pipelining ......................149 Pipelines..........................149 Parallel-Executability ....................... 156 Execution Cycles and Pipeline Stalling ................160 Section 9 Power-Down Modes ..................
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10.8 BRAF ..BRAnch Far ..........Branch Instruction....213 10.9 BSR ..... Branch to SubRoutine ......Branch Instruction....214 10.10 BSRF ... Branch to SubRoutine Far ......Branch Instruction....216 10.11 BT ....Branch if True .........Branch Instruction....218 10.12 BT/S ..... Branch if True with delay Slot ....Branch Instruction....220 10.13 CLRMAC..
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10.47 FTRV ..Floating-point TRansform Vector ..Floating-Point Instruction ..292 10.48 JMP ..... JuMP ............Branch Instruction....295 10.49 JSR ....Jump to SubRoutine .......Branch Instruction....296 10.50 LDC ..... LoaD to Control register ......System Control Instruction ... 298 10.51 LDS ..... LoaD to FPU System register ....System Control Instruction ... 302 10.52 LDS .....
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10.90 SHLRn ..n bits SHift Logical Right .......Shift Instruction..... 365 10.91 SLEEP ..SLEEP ............System Control Instruction ... 367 10.92 STC ..... STore Control register ......System Control Instruction ... 368 10.93 STS ....STore System register ......System Control Instruction ... 373 10.94 STS ....
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Rev. 2.0, 03/99, page xiv of 13...
Page 15: Section 1 Overview

MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The SH7750 has an on-chip bus state controller (BSC) that allows direct connection to DRAM and synchronous DRAM without external circuitry. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
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External buses  Separate 26-bit address and 64-bit data buses  External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency • Original Hitachi SH architecture • 32-bit internal data bus • General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers) ...
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Table 1.1 SH7750 Features (cont) Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 •...
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Table 1.1 SH7750 Features (cont) Item Features • Clock pulse Choice of main clock: 1/2, 1, 3, or 6 times EXTAL generator (CPG) • Clock modes:  CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock: maximum 200 MHz ...
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Table 1.1 SH7750 Features (cont) Item Features • Cache memory Instruction cache (IC)  8 kbytes, direct mapping  256 entries, 32-byte block length  Normal mode (8-kbyte cache)  Index mode • Operand cache (OC)  16 kbytes, direct mapping ...
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Table 1.1 SH7750 Features (cont) Item Features • Bus state Supports external memory access controller (BSC)  64/32/16/8-bit external data bus • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: ...
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Table 1.1 SH7750 Features (cont) Item Features • Serial Two full-duplex communication channels (SCI, SCIF) communication • Channel 1 (SCI): interface  Choice of asynchronous mode or synchronous mode (SCI, SCIF)  Supports smart card interface • Channel 2 (SCIF): ...
Page 22: Block Diagram

Block Diagram Figure 1.1 shows an internal block diagram of the SH7750. Lower 32-bit data Lower 32-bit data I cache O cache ITLB UTLB (8 kB) (16 kB) INTC DMAC (SCIF) External bus interface 26-bit 64-bit address data CCN: Cache and TLB controller...
Page 23: Section 2 Programming Model

Section 2 Programming Model Data Formats The data formats handled by the SH7750 are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 24: Register Configuration

2.2.1 Privileged Mode and Banks Processor Modes: The SH7750 has two processor modes, user mode and privileged mode. The SH7750 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed...
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Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.
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R0 _ BANK0* R0 _ BANK1* R0 _ BANK0* R1 _ BANK0* R1 _ BANK1* R1 _ BANK0* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK0* R3 _ BANK1* R4 _ BANK0* R4 _ BANK0* R4 _ BANK1* R5 _ BANK0* R5 _ BANK0*...
Page 27: General Registers

32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one processor mode. The SH7750 has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
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SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...
Page 29: Floating-point Registers

2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
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• Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10...
Page 31: Control Registers

Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX) 31 30 29 28 27 16 15 14 —...
Page 32: System Registers

Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
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Floating-point status/control register, FPSCR (32 bits, initial value = H’0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 34: Memory-mapped Registers

This area must be accessed in address translation mode using the TLB. Since external memory is defined as a 29-bit address space in the SH7750 architecture, the TLB’s physical page numbers do not cover a 32-bit address space. In address translation, the page numbers of this area can be set in the corresponding field of the TLB by accessing a memory-mapped register.
Page 35: Data Format In Registers, Data Formats In Memory

Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Longword Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.
Page 36: Processor States

Note: The SH7750 does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. Processor States The SH7750 has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state.
Page 37: Processor Modes

From any state when From any state when = 0 and = 0 and Power-on reset state Manual reset state = 0, Reset state = 1, = 1, Exception-handling state Bus request Bus request clearance Interrupt Interrupt Exception End of exception Bus-released state interrupt transition...
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Rev. 2.0, 03/98, page 24 of 396...
Page 39: Section 3 Memory Management Unit (mmu)

3.1.1 Features The SH7750 can handle 29-bit external memory space from an 8-bit address space identifier and 32-bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH7750. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB).
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(usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7750 is referred to as virtual address space, and the address space in physical memory as physical address space.
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Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev.
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3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Name tion Value* Address* Address* Size Page table entry high PTEH Undefined H’FF00 0000 H’1F00 0000 32 register Page table entry low PTEL Undefined H’FF00 0004 H’1F00 0004 32...
Page 43: Register Descriptions

Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.
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1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H’FF00 0000 in the P4 area and H’1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware.
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P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated by hardware. • LRUI: The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss.
Page 46: Memory Space

3.3.1 Physical Memory Space The SH7750 supports a 32-bit physical memory space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical memory space. The physical memory space is divided into a number of areas, as shown in figure 3.3.
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P4 Area: The P4 area is mapped onto SH7750 on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4.
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H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000 Operand cache data array H'F600 0000...
Page 49: External Memory Space

3.3.2 External Memory Space The SH7750 supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC), in the Hardware Manual.
Page 50: Virtual Memory Space

Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH7750 to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.
Page 51: On-chip Ram Space

3.3.4 On-Chip RAM Space In the SH7750, half (8 kbytes) of the instruction cache (16 kbytes) can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H’7C00 0000 to H’7FFF FFFF are an on-chip RAM area.
Page 52: Tlb Functions

3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined.
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Entry 0 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 1 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 2 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 63 ASID [7:0] VPN [31:10] V...
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• ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed.
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• C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1.
Page 56: Instruction Tlb (itlb) Configuration

3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries.
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Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match...
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Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match VPNs match...
Page 59: Mmu Functions

A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7750 copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.
Page 60: Hardware Itlb Miss Handling

3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7750 searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This procedure is known as hardware ITLB miss handling.
Page 61: Avoiding Synonym Problems

This problem does not occur with the instruction TLB or instruction cache . In the SH7750, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4-kbyte page, are subject to address translation.
Page 62: Mmu Exceptions

MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 63: Instruction Tlb Miss Exception

3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below.
Page 64: Instruction Tlb Protection Violation Exception

3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.
Page 65: Data Tlb Multiple Hit Exception

3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.
Page 66: Data Tlb Protection Violation Exception

Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry.
Page 67: Initial Page Write Exception

Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains...
Page 68: Memory-mapped Tlb Configuration

Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3.
Page 69: Itlb Address Array

3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H’F200 0000 to H’F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field.
Page 70: Itlb Data Array 1

3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H’F300 0000 to H’F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.
Page 71: Itlb Data Array 2

3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H’F380 0000 to H’F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
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In the address field, bits [31:24] have the value H’F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0].
Page 73: Utlb Data Array 1

3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H’F700 0000 to H’F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field.
Page 74: Utlb Data Array 2

3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H’F780 0000 to H’F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 75: Section 4 Caches

4.1.1 Features The SH7750 has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) can also be used as on- chip RAM. The features of these caches are summarized in table 4.1.
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4.1.2 Register Configuration Table 4.2 shows the cache control registers. Table 4.2 Cache Control Registers Initial Area 7 Access Name Abbreviation R/W Value* Address* Address* Size Cache control H’0000 0000 H’FF00 001C H’1F00 001C register Queue address QACR0 Undefined H’FF00 0038 H’1F00 0038 control register 0 Queue address...
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(1) Cache Control Register (CCR): CCR contains the following bits: IIX: IC index enable ICI: IC invalidation ICE: IC enable OIX: OC index enable ORA: OC RAM enable OCI: OC invalidation Copy-back enable Write-through enable OCE: OC enable Longword access to CCR can be performed from H’FF00 001C in the P4 area and H’1F00 001C in area 7.
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• OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode •...
Page 79: Operand Cache (oc)

Operand Cache (OC) 4.3.1 Configuration Figure 4.2 shows the configuration of the operand cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 RAM area determination [11:5] [13] [12] Longword (LW) selection Address array Data array Tag address 19 bits 1 bit 1 bit...
Page 80: Read Operation

The operand cache consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32- byte data. • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 81: Write Operation

3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address.
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3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. 3b.
Page 83: Write-back Buffer

4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, the SH7750 has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination.
Page 84: Oc Index Mode

• When OC index mode is off (CCR.OIX = 0) H’7C00 0000 to H’7C00 0FFF (4 kB): Corresponds to RAM area 1 H’7C00 1000 to H’7C00 1FFF (4 kB): Corresponds to RAM area 1 H’7C00 2000 to H’7C00 2FFF (4 kB): Corresponds to RAM area 2 H’7C00 3000 to H’7C00 3FFF (4 kB): Corresponds to RAM area 2 H’7C00 4000 to H’7C00 4FFF (4 kB): Corresponds to RAM area 1 RAM areas 1 and 2 then repeat every 8 kbytes up to H’7FFF FFFF.
Page 85: Coherency Between Cache And External Memory

Prefetch Operation The SH7750 supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance.
Page 86: Instruction Cache (ic)

Instruction Cache (IC) 4.4.1 Configuration Figure 4.5 shows the configuration of the instruction cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 [11:5] [12] Longword (LW) selection Address array Data array Tag address 19 bits 1 bit 32 bits 32 bits...
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The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32- byte data (16 instructions). • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 88: Ic Index Mode

4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address; therefore, when 8 kbytes or more of consecutive program instructions are handled, the IC is fully used by this program.
Page 89: Ic Data Array

2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3.
Page 90: Oc Address Array

1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field.
Page 91

The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0.
Page 92: Oc Data Array

4.5.4 OC Data Array The OC data array is allocated to addresses H’F500 0000 to H’F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field.
Page 93: Store Queues

Store Queues Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory. 4.6.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.10. These two store queues can be set independently. SQ0[0] SQ0[1] SQ0[2]...
Page 94

• When MMU is on The SQ area (H’E000 0000 to H’E3FF FFFF) is set in VPN of the UTLB, and the transfer destination external memory address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page.
Page 95: Sq Protection

4.6.4 SQ Protection It is possible to set protection against SQ writes and transfers to external memory. If an SQ write violates the protection setting, an exception will be generated but the SQ contents will be corrupted. If a transfer from the SQs to external memory (prefetch instruction) violates the protection setting, the transfer to external memory will be inhibited and an exception will be generated.
Page 96

Rev. 2.0, 03/99, page 82 of 396...
Page 97: Section 5 Exceptions

SH7750 exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1.
Page 98

Register Descriptions There are three registers related to exception handling. These are allocated to memory, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H’FF00 0024, and contains a 12- bit exception code.
Page 99: Exception Handling Functions

Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception.
Page 100: Exception Types And Priorities

Offset Code Reset Abort type Power-on reset H’A000 0000 — H’000 Manual reset H'A000 0000 — H’020 Hitachi-UDI reset H'A000 0000 — H’000 Instruction TLB multiple-hit H'A000 0000 — H’140 exception Data TLB multiple-hit exception 1 H'A000 0000 — H’140...
Page 101

(VBR) H'600 H'400 module TMU1 TUNI1 H'420 interrupt TMU2 TUNI2 H'440 (module/ source) TICPI2 H'460 H'480 H'4A0 H'4C0 H'4E0 H'500 H'520 H'540 H'560 RCMI H'580 ROVI H'5A0 Hitachi-UDI Hitachi- H'600 GPIO GPIOI H'620 Rev. 2.0, 03/99, page 87 of 396...
Page 102: Exception Flow

Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral DMAC DMTE0 (VBR) H’600 H’640 type module DMTE1 H’660 interrupt DMTE2 H’680 (module/ source) DMTE3 H’6A0 DMAE H’6C0 SCIF H’700 H’720 H’740...
Page 103: Exception Source Acceptance

Reset requested? Execute next instruction Is highest- General priority exception exception requested? re-exception type? Cancel instruction execution result Interrupt requested? SSR ← SR EXPEVT ← exception code SPC ← PC SR. {MD, RB, BL, FD, IMASK} ← 11101111 SGR ← R15 PC ←...
Page 104

Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Instruction fetch ID: Instruction decode EX: Instruction execution Instruction n+3 MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling:...
Page 105: Exception Requests And Bl Bit

5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU’s internal registers are set to their post-reset state, the registers of the other modules retain their contents prior to the exception, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 106: Description Of Exceptions

Description of Exceptions The various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made. 5.6.1 Resets (1) Power-On Reset • Sources:  SCK2 pin high level and pin low level ...
Page 107

(2) Manual Reset • Sources:  SCK2 pin low level and pin low level  When a general exception other than a user break occurs while the BL bit is set to 1 in SR  When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
Page 108

(3) Hitachi-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000.
Page 109

(4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H’A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 110

(5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H’A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 111: General Exceptions

5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H’0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 112

(2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H’0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 113

(3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H’0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 114

(4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible Read/write access possible...
Page 115

(5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H’0000 0100 •...
Page 116

(6) Data Address Error • Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)  Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ...
Page 117

(7) Instruction Address Error • Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 118

(8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H’0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR when the TRAPA instruction is executed are saved in SSR.
Page 119

(9) General Illegal Instruction Exception • Sources:  Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H’FFFD  Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 120

(10) Slot Illegal Instruction Exception • Sources:  Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H’FFFD  Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR ...
Page 121

(11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H’0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 122

(12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H’0000 0100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR contents when this exception occurred are saved in SSR.
Page 123

(13) User Breakpoint Trap • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H’0000 0100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 124

(14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H’0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 125: Interrupts

5.6.3 Interrupts (1) NMI • Source: NMI pin edge detection • Transition address: VBR + H’0000 0600 • Transition operations: The PC and SR contents for the instruction at which this exception is accepted are saved in SPC and SSR. Exception code H’1C0 is set in INTEVT.
Page 126

(2) IRL Interrupts • Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'0000 0600 • Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC.
Page 127

(3) Peripheral Module Interrupts • Source: The interrupt mask bit setting in SR is smaller than the peripheral module (Hitachi- UDI, GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary).
Page 128: Priority Order With Multiple Exceptions

5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 129: Usage Notes

Usage Notes 1. Return from exception handling a. Check the BL bit in SR with software. If SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR contents are set in SR, and branch is made to the SPC address to return from the exception handling routine.
Page 130

• When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register. Note: * See section 20.4 in the SH-4 Hardware manual.
Page 131: Section 6 Floating-point Unit

A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) The SH7750 can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 23 22 Figure 6.1 Format of Single-Precision Floating-Point Number...
Page 132

52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1. The two values E –...
Page 133: Non-numbers (nan)

Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H’7FFFFFFF to H’7FC00000 H’7FFFFFFF H’FFFFFFFF to H’7FF80000 H’00000000 Quiet non-number H’7FBFFFFF to H’7F800001 H’7FF7FFFF H’FFFFFFFF to H’7FF00000 H’00000001 Positive infinity H’7F800000 H’7FF00000 H’00000 Positive normalized H’7F7FFFFF to H’00800000 H’7FEFFFFF H’FFFFFFFF to number H’00100000 H’00000000 Positive denormalized...
Page 134: Denormalized Numbers

EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7750 as operation results are as follows: • Single-precision qNaN: H’7FBFFFFF •...
Page 135: Registers

Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;...
Page 136

FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14 FPR15_BANK0 FR15 XF15 FPR0_BANK1...
Page 137: Floating-point Status/control Register (fpscr)

6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H’0004 0001) • FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1– FPR15_BANK1 are assigned to XF0–XF15. FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1– FPR15_BANK1 are assigned to FR0–FR15.
Page 138: Floating-point Communication Register (fpul)

• Bits 22 to 31: Reserved These bits are always read as 0, and should only be written with 0. Notes: The following functions have been added to the FPU of the SH7750 (not provided in the FPU of the SH7718): 1.
Page 139: Floating-point Exceptions

0, but the corresponding bit in the flag field remains unchanged. • Enable/disable exception handling The SH7750 supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases:  FPU error (E): FPSCR.DN = 0 and a denormalized number is input ...
Page 140: Graphics Support Functions

Geometric Operation Instructions Geometric operation instructions perform approximate-value computations. To enable high-speed computation with a minimum of hardware, the SH7750 ignores comparatively small values in the partial computation results of four multiplications. Consequently, the error shown below is produced in the result of the computation:...
Page 141

The number of significant digits is 24 for a normalized number and 23 for a denormalized number (number of leading zeros in the fractional part). In future version of SH series, the above error is guaranteed, but the same result as SH7750 is not guaranteed.
Page 142: Pair Single-precision Data Transfer

In addition to the powerful new geometric operation instructions, the SH7750 also supports high- speed data transfer instructions. When FPSCR.SZ = 1, the SH7750 can perform data transfer by means of pair single-precision data transfer instructions. • FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) •...
Page 143: Section 7 Instruction Set

When a double-precision floating- point operation is specified (FPSCR.PR = 1), the result of an operation using quadword access will be undefined. When the SH7750 moves byte-size or word-size data from memory to a register, the data is sign-extended.
Page 144

In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution.
Page 145: Addressing Modes

Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 146

Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), Word: Rn +...
Page 147

Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size.
Page 148

Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp × 2 → Branch- disp added after being sign-extended and multiplied by 2.
Page 149: Instruction Set

Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand →, ← Summary of Transfer direction operation...
Page 150

Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — (disp × 2 + PC + 4) → sign MOV.W @(disp,PC),Rn 1001nnnndddddddd — — extension → Rn (disp × 4 + PC & H'FFFFFFFC MOV.L @(disp,PC),Rn 1101nnnndddddddd —...
Page 151

Table 7.3 Fixed-Point Transfer Instructions (cont) Instruction Operation Instruction Code Privileged T Bit R0 → (disp + GBR) MOV.B R0,@(disp,GBR) 11000000dddddddd — — R0 → (disp × 2 + GBR) MOV.W R0,@(disp,GBR) 11000001dddddddd — — R0 → (disp × 4 + GBR) MOV.L R0,@(disp,GBR) 11000010dddddddd —...
Page 152

Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100 — — Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii — — Rn + Rm + T → Rn, carry → T ADDC Rm,Rn 0011nnnnmmmm1110 —...
Page 153

Table 7.4 Arithmetic Operation Instructions (cont) Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word → Rn EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte → Rn EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 —...
Page 154

Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —...
Page 155

Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — LSB → Rn → T ROTR 0100nnnn00000101 — T ← Rn ← T ROTCL 0100nnnn00100100 — T → Rn → T ROTCR 0100nnnn00100101 —...
Page 156

Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — 4 → PC When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd —...
Page 157

Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit 0 → MACH, MACL CLRMAC 0000000000101000 — — 0 → S CLRS 0000000001001000 — — 0 → T CLRT 0000000000001000 — Rm → SR Rm,SR 0100mmmm00001110 Privileged Rm → GBR Rm,GBR 0100mmmm00011110 —...
Page 158

Table 7.8 System Control Instructions (cont) Instruction Operation Instruction Code Privileged T Bit 1 → S SETS 0000000001011000 — — 1 → T SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR → Rn SR,Rn 0000nnnn00000010 Privileged — GBR →...
Page 159

Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H’00000000 → FRn FLDI0 1111nnnn10001101 — — H'3F800000 → FRn FLDI1 1111nnnn10011101 — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — — (Rm) → FRn FMOV.S @Rm,FRn 1111nnnnmmmm1000 — —...
Page 160

Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H’7FFF FFFF FFFF 1111nnn001011101 — — FFFF → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 — — When DRn = DRm, 1 → T FCMP/EQ DRm,DRn 1111nnn0mmm00100 —...
Page 161

Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn 1111nnn1mmm01100 — — XDm → DRn FMOV XDm,DRn 1111nnn0mmm11100 — — XDm → XDn FMOV XDm,XDn 1111nnn1mmm11100 — — (Rm) → XDn FMOV @Rm,XDn 1111nnn1mmmm1000 —...
Page 162

Rev. 2.0, 03/99, page 148 of 396...
Page 163: Section 8 Pipelining

Section 8 Pipelining The SH7750 is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7750.
Page 164

1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction • Address •...
Page 165

1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.
Page 166

10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. CR definition: 1 issue cycle LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.
Page 167

19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.
Page 168

31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.
Page 169

40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle : Cannot overlap a stage of the same kind, except when two instructions are Notes: executed in parallel.
Page 170: Parallel-executability

Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.
Page 171

Table 8.1 Instruction Groups (cont) 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W...
Page 172

Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV...
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Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L...
Page 174: Execution Cycles And Pipeline Stalling

Table 8.2 Parallel-Executability 2nd Instruction Instruction O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: •...
Page 175

The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 176

Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)).
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(a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction. (b) Parallel execution: parallel-executable and no dependency 1 issue cycle EX-group ADD and LS-group MOV.L can...
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(e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result MOV.L @R1,R1 of ADD as its destination address.
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(e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,R1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency 11-cycle latency FSQRT FR4 FMOV FR0,FR4 10 stall cycles = latency (11) - 1 The registers are written-back in program order.
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(h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR GBR,R2 3 stall cycles FADD DR0,DR2 MAC.W @R1+,@R2+ 5 stall cycles...
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Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Data EXTS.B Rm,Rn — — — transfer EXTS.W Rm,Rn — — — instructions EXTU.B Rm,Rn — — — EXTU.W Rm,Rn —...
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Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Data MOV.W R0,@(disp,Rn) — — — transfer MOV.L Rm,@(disp,Rn) — — — instructions MOV.B Rm,@(R0,Rn) — — — MOV.W Rm,@(R0,Rn) —...
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Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn — — — MAC.L @Rm+,@Rn+ 2/2/4/4...
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Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — — — SHAD Rm,Rn —...
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Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS — — — SETT —...
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Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn — — — SPC,Rn —...
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Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Single- FABS — — — precision FADD FRm,FRn — — — floating-point FCMP/EQ FRm,FRn — — — instructions FCMP/GT FRm,FRn —...
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Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Double- FNEG — — — precision FSQRT (23, 24)/ floating-point instructions FSUB DRm,DRn (7, 8)/9 FTRC DRm,FPUL FPU system Rm,FPUL —...
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4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6.
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Rev. 2.0, 03/99, page 176 of 396...
Page 191: Section 9 Power-down Modes

Section 9 Power-Down Modes Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: •...
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Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status Power- On-chip Down Entering On-Chip Peripheral External Exiting Mode Conditions CPG Memory Modules Pins Memory Method Refreshing • Interrupt Sleep SLEEP Operating Halted Held Operating Held instruction (registers •...
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9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Initial Area 7 Access Name Abbreviation Value P4 Address Address Size Standby control register STBCR H’00 H’FFC00004 H’1FC00004 Standby control register 2 STBCR2 H’00 H’FFC00010 H’1FC00010 Register Descriptions...
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Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral module related pins in the input or high-impedance state. For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control.
Page 195: Peripheral Module Pin High Impedance Control

Bit 1—Module Stop 1 (MSTP1): Specifies stopping of the clock supply to the realtime clock (RTC) among the on-chip peripheral modules. The clock supply to the RTC is stopped when the MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the counters continue to operate.
Page 196: Peripheral Module Pin Pull-up Control

9.2.3 Peripheral Module Pin Pull-Up Control When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins are pulled up when in the input or high-impedance state. • Relevant Pins SCI related pins MD0/SCK MD1/TXD2 MD2/RXD2 MD7/TXD...
Page 197: Sleep Mode

Sleep Mode 9.3.1 Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Page 198: Standby Mode

Standby Mode 9.5.1 Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU.
Page 199: Exit From Standby Mode

9.5.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the pin. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, , or on-chip peripheral module (except interval timer) interrupt is detected, the WDT starts counting.
Page 200: Module Standby Function

Module Standby Function 9.6.1 Transition to Module Standby Function Setting the MSTP4–MSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.
Page 201: Section 10 Instruction Descriptions

Section 10 Instruction Descriptions Instructions are listed in this section in alphabetical order. The following format is used for the instruction descriptions. Instruction Name Full Name Instruction Type Function (Indication of delayed branch instruction or interrupt-disabling instruction) Execution Format Summary of Operation Instruction Code States T Bit...
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unsigned char Read_Byte(unsigned long Addr); unsigned short Read_Word(unsigned long Addr); unsigned long Read_Long(unsigned long Addr); These reflect the respective sizes of address Addr. A word read from other than a 2n address, or a longword read from other than a 4n address, will be detected as an address error. unsigned char Write_Byte(unsigned long Addr, unsigned long Data);...
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Error( char *er ); Error display function These are floating-point number definition statements. #define PZERO #define NZERO #define DENORM #define NORM #define PINF #define NINF #define qNaN #define sNaN #define EQ #define GT #define LT #define UO #define INVALID #define FADD #define FSUB #define CAUSE 0x0003f000...
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#define FPSCR_I FPSCR>>12&1 #define FPSCR_RM FPSCR&1 #define FR_HEX frf.l[ FPSCR_FR] #define FR frf.f[ FPSCR_FR] #define DR frf.d[ FPSCR_FR] #define XF_HEX frf.l[~FPSCR_FR] #define XF frf.f[~FPSCR_FR] #define XD frf.d[~FPSCR_FR] union { l[2][16]; float f[2][16]; double d[2][8]; }frf; int FPSCR; int sign_of(int n) return(FR_HEX[n]>>31);...
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else return(sNaN); /* Double-precision */ else { if(abs < 0x00100000){ if((FPSCR_DN == 1) || ((abs == 0x00000000) && (FR_HEX[n+1] == 0x00000000)){ if(sign_of(n) == 0) {zero(n, 0); return(PZERO);} else {zero(n, 1); return(NZERO);} else return(DENORM); else if(abs < 0x7ff00000) return(NORM); else if((abs == 0x7ff00000) && (FR_HEX[n+1] == 0x00000000)) { if(sign_of(n) == 0) return(PINF);...
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1-bit sign long double x; 15-bit exponent int l[4]; 112-bit mantissa */ dstx; if(FPSCR_PR == 0) { if(type == FADD) srcf.f = FR[m]; else srcf.f = -FR[m]; dstd.d = FR[n]; /* Conversion from single-precision to double-precision */ dstd.d += srcf.f; if(((dstd.d == FR[n]) &&...
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if((dstx.l[2] & 0x0fffffff) || dstx.l[3]) set_I(); dst.d += srcd.d; /* Round to nearest */ if(FPSCR_RM == 1) { dstx.l[2] &= 0xf0000000; /* Round to zero */ dstx.l[3] = 0x00000000; dst.d = dstx.x; check_double_exception(&DR[n>>1] ,dst.d); void normal_fmul(int m,n) union { float f; int l;...
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tmpx.x *= DR[m>>1]; /* Precise creation */ tmpd.d *= DR[m>>1]; /* Round to nearest */ if(tmpd.d != tmpx.x) set_I(); if(tmpd.d > tmpx.x) && (FPSCR_RM == 1)) { tmpd.l[1] -= 1; /* Round to zero */ if(tmpd.l[1] == 0xffffffff) tmpd.l[0] -= 1; check_double_exception(&DR[n>>1], tmpd.d);...
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else if(data_type_of(m+i) == NZERO) FR[m+i] = -0.0; (data_type_of(n+i) == PZERO) FR[n+i] = +0.0; else if(data_type_of(n+i) == NZERO) FR[n+i] = -0.0; mlt[i].d = FR[m+i]; mlt[i].d *= FR[n+i]; /* To be precise, with FIPR, the lower 18 bits are discarded; therefore, this description is simplified, and differs from the hardware.
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if(abs < tmp.f) { if((FPSCR_DN == 1) && (abs != 0.0)) { set_I(); if(result < 0.0) result = -0.0; /* Zeroize denormalized number */ else result = 0.0; if(FPSCR_I == 1) set_U(); if(FPSCR & ENABLE_OUI) fpu_exception_trap(); else *dst = result; void check_double_exception(double *dst,result) union { double d;...
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/* Zeroize denormalized number */ else result = 0.0; if(FPSCR_I == 1) set_U(); if(FPSCR & ENABLE_OUI) fpu_exception_trap(); else *dst = result; int check_product_invalid(int m,n) return(check_product_infinity(m,n) && ((data_type_of(m) == PZERO) || (data_type_of(n) == PZERO) || (data_type_of(m) == NZERO) || (data_type_of(n) == NZERO))); int check_ product_infinity(int m,n) return((data_type_of(m) == PINF) || (data_type_of(n) == PINF) || (data_type_of(m) == NINF) || (data_type_of(n) == NINF));...
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void clear_cause () {FPSCR &= ~CAUSE;} void set_E() {FPSCR |= SET_E; fpu_exception_trap();} void set_V() {FPSCR |= SET_V;} void set_Z() {FPSCR |= SET_Z;} void set_O() {FPSCR |= SET_O;} void set_U() {FPSCR |= SET_U;} void set_I() {FPSCR |= SET_I;} void invalid(int n) set_V();...
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void qnan(int n) if (FPSCR_PR==0) FR[n] = 0x7fbfffff; else { FR[n] = 0x7ff7ffff; FR[n+1] = 0xffffffff; Example An example is shown using assembler mnemonics, indicating the states before and after execution of the instruction. Italics (e.g., .align) indicate an assembler control instruction. The meaning of the assembler control instructions is given below.
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10.1 ADD binary Arithmetic Instruction Binary Addition Execution Format Summary of Operation Instruction Code States T Bit Rn+Rm → Rn ADD Rm,Rn 0011nnnnmmmm1100 1 — Rn+imm → Rn ADD #imm,Rn 0111nnnniiiiiiii 1 — Description This instruction adds together the contents of general registers Rn and Rm and stores the result in 8-bit immediate data can also be added to the contents of general register Rn.
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Example ;Before execution R0 = H’7FFFFFFF, R1 = H’00000001 R0,R1 ;After execution R1 = H’80000000 ;Before execution R2 = H’00000000 #H’01,R2 ;After execution R2 = H’00000001 ;Before execution R3 = H’00000001 #H’FE,R3 ;After execution R3 = H’FFFFFFFF Rev. 2.0, 03/99, page 201 of 396...
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10.2 ADDC ADD with Carry Arithmetic Instruction Binary Addition with Carry Execution Format Summary of Operation Instruction Code States T Bit Rn+Rm+T → Rn, carry → T 0011nnnnmmmm1110 1 ADDC Rm,Rn Carry Description This instruction adds together the contents of general registers Rn and Rm and the T bit, and stores the result in Rn.
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10.3 ADDV ADD with (V flag) overflow check Arithmetic Instruction Binary Addition with Overflow Check Execution Format Summary of Operation Instruction Code States T Bit Rn+Rm → Rn, ADDV Rm,Rn 0011nnnnmmmm1111 1 Overflow overflow → T Description This instruction adds together the contents of general registers Rn and Rm and stores the result in Rn.
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Example ;Before execution R0 = H’00000001, R1 = H’7FFFFFFE, T=0 ADDV R0,R1 ;After execution R1 = H’7FFFFFFF, T=0 ;Before execution R0 = H’00000002, R1 = H’7FFFFFFE, T=0 ADDV R0,R1 ;After execution R1 = H’80000000, T=1 Rev. 2.0, 03/99, page 204 of 396...
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10.4 AND logical Logical Instruction Logical AND Execution Format Summary of Operation Instruction Code States T Bit Rm & Rm → Rn Rm,Rn 0010nnnnmmmm1001 1 — R0 & imm → R0 #imm,R0 11001001iiiiiiii 1 — AND.B #imm,@(R0,GBR) (R0+GBR) & imm → 11001101iiiiiiii 4 —...
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temp&=(0x000000FF & (long)i); Write_Byte(GBR+R[0],temp); PC+=2; Example ;Before execution R0 = H’AAAAAAAA, R1=H’55555555 R0,R1 ;After execution R1 = H’00000000 ;Before execution R0 = H’FFFFFFFF #H’0F,R0 ;After execution R0 = H’0000000F #H’80,@(R0,GBR) ;Before execution (R0,GBR) = H’A5 AND.B ;After execution (R0,GBR) = H’80 Rev.
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10.5 Branch if False Branch Instruction Conditional Branch Execution Format Summary of Operation Instruction Code States T Bit BF label If T = 0 10001011dddddddd 1 — PC + 4 + disp × 2 → PC If T = 1, nop Description This is a conditional branch instruction that references the T bit.
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Example ;Normally T = 0 CLRT ;T = 0, so branch is not taken. TRGET_T ;T = 0, so branch to TRGET_F. TRGET_F ;← BF instruction branch destination TRGET_F: Rev. 2.0, 03/99, page 208 of 396...
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10.6 BF/S Branch if False with delay Slot Branch Instruction Conditional Branch with Delay Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit BF/S label If T = 0 10001111dddddddd 1 — PC + 4 + disp × 2 → PC If T = 1, nop Description This is a delayed conditional branch instruction that references the T bit.
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Operation BFS(int d) /* BFS disp */ int disp; unsigned int temp; temp=PC; if ((d&0x80)==0) disp=(0x000000FF & d); else disp=(0xFFFFFF00 | d); if (T==0) PC=PC+4+(disp<<1); else PC+=4; Delay_Slot(temp+2); Example ;Normally T = 0 CLRT ;T = 0, so branch is not taken. BT/S TRGET_T ;T = 0, so branch to TRGET.
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10.7 BRAnch Branch Instruction Unconditional Branch Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit PC+4+disp×2 → PC BRA label 1010dddddddddddd 1 — Description This is an unconditional branch instruction. The branch destination is address (PC + 4 + displacement ×...
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Example ;Branch to TRGET. TRGET ;ADD executed before branch. R0,R1 ;← BRA instruction branch destination TRGET: Rev. 2.0, 03/99, page 212 of 396...
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10.8 BRAF BRAnch Far Branch Instruction Unconditional Branch Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit PC+4+Rn → PC BRAF Rn 0000nnnn00100011 2 — Description This is an unconditional branch instruction. The branch destination is address (PC + 4 + Rn). The branch destination address is the result of adding 4 plus the 32-bit contents of general register Rn to PC.
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10.9 Branch to SubRoutine Branch Instruction Branch to Subroutine Procedure Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit PC+4 → PR, BSR label 1011dddddddddddd 1 — PC+4+disp×2 → PC Description This instruction branches to address (PC + 4 + displacement × 2), and stores address (PC + 4) in PR.
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Example ;Branch to TRGET. TRGET ;MOV executed before branch. R3,R4 ;Subroutine procedure return destination (contents of PR) R0,R1 ..;← Entry to procedure TRGET: R2,R3 ;Return to above ADD instruction. ;MOV executed before branch. #1,R0 Rev. 2.0, 03/99, page 215 of 396...
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10.10 BSRF Branch to SubRoutine Far Branch Instruction Branch to Subroutine Procedure Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit PC+4 → PR, BSRF Rn 0000nnnn00000011 2 — PC+4+Rn → PC Description This instruction branches to address (PC + 4 + Rn), and stores address (PC + 4) in PR. The PC source value is the BSRF instruction address.
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Example #(TRGET-BSRF_PC),R0 ;Set displacement. MOV.L ;Branch to TRGET. BSRF ;MOV executed before branch. R3,R4 BSRF_PC: R0,R1 ..;← Entry to procedure TRGET: R2,R3 ;Return to above ADD instruction. ;MOV executed before branch. #1,R0 Rev. 2.0, 03/99, page 217 of 396...
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10.11 Branch if True Branch Instruction Conditional Branch Execution Format Summary of Operation Instruction Code States T Bit BT label If T = 1 10001001dddddddd 1 — PC + 4 + disp × 2 → PC If T = 0, nop Description This is a conditional branch instruction that references the T bit.
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Example ;Normally T = 1 SETT ;T = 1, so branch is not taken. TRGET_F ;T = 1, so branch to TRGET_T. TRGET_T ;← BT instruction branch destination TRGET_T: Rev. 2.0, 03/99, page 219 of 396...
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10.12 BT/S Branch if True with delay Slot Branch Instruction Conditional Branch with Delay Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit BT/S label If T = 1 10001101dddddddd 1 — PC + 4 + disp × 2 → PC If T = 0, nop Description This is a conditional branch instruction that references the T bit.
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Operation BTS(int d) /* BTS disp */ int disp; unsigned temp; temp=PC; if ((d&0x80)==0) disp=(0x000000FF & d); else disp=(0xFFFFFF00 | d); if (T==1) PC=PC+4+(disp<<1); else PC+=4; Delay_Slot(temp+2); Example ;Normally T = 1 SETT ;T = 1, so branch is not taken. BF/S TRGET_F ;T = 1, so branch to TRGET_T.
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10.13 CLRMAC CleaR MAC register System Control Instruction MAC Register Clear Execution Format Summary of Operation Instruction Code States T Bit 0 → MACH, MACL CLRMAC 0000000000101000 1 — Description This instruction clears the MACH and MACL registers. Operation CLRMAC( ) /* CLRMAC */ MACH=0;...
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10.14 CLRS CleaR S bit System Control Instruction S Bit Clear Execution Format Summary of Operation Instruction Code States T Bit 0 → S CLRS 0000000001001000 1 — Description This instruction clears the S bit to 0. Operation CLRS( ) /* CLRS */ S=0;...
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10.15 CLRT CleaR T bit System Control Instruction T Bit Clear Execution Format Summary of Operation Instruction Code States T Bit 0 → T CLRT 0000000000001000 1 Description This instruction clears the T bit. Operation CLRT( ) /* CLRT */ T=0;...
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10.16 CMP/cond CoMPare conditionally Arithmetic Instruction Compare Execution Format Summary of Operation Instruction Code States T Bit If Rn = Rm, 1 → T CMP/EQ Rm,Rn 0011nnnnmmmm0000 1 Result of comparison If Rn ≥ Rm, signed, 1 → T CMP/GE Rm,Rn 0011nnnnmmmm0011 1 Result of...
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Mnemonic Description CMP/EQ Rm,Rn If Rn = Rm, T = 1 If Rn ≥ Rm as signed values, T = 1 CMP/GE Rm,Rn CMP/GT Rm,Rn If Rn > Rm as signed values, T = 1 CMP/HI Rm,Rn If Rn > Rm as unsigned values, T = 1 If Rn ≥...
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PC+=2; CMPHS(long m, long n) /* CMP_HS Rm,Rn */ if ((unsigned long)R[n]>=(unsigned long)R[m]) T=1; else T=0; PC+=2; CMPPL(long n) /* CMP_PL Rn */ if ((long)R[n]>0) T=1; else T=0; PC+=2; CMPPZ(long n) /* CMP_PZ Rn */ if ((long)R[n]>=0) T=1; else T=0; PC+=2;...
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PC+=2; CMPIM(long i) /* CMP_EQ #imm,R0 */ long imm; if ((i&0x80)==0) imm=(0x000000FF & (long i)); else imm=(0xFFFFFF00 | (long i)); if (R[0]==imm) T=1; else T=0; PC+=2; Example ;R0 = H’7FFFFFFF, R1 = H’80000000 CMP/GE R0,R1 ;T = 0, so branch is not taken. TRGET_T ;R0 = H’7FFFFFFF, R1 = H’80000000 CMP/HS...
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10.17 DIV0S DIVide (step 0) as Signed Arithmetic Instruction Initialization for Signed Division Execution Format Summary of Operation Instruction Code States T Bit MSB of Rn → Q, DIV0S Rm,Rn 0010nnnnmmmm0111 1 Result of MSB of Rm → M, calculation M^Q →...
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10.18 DIV0U DIVide (step 0) as Unsigned Arithmetic Instruction Initialization for Unsigned Division Execution Format Summary of Operation Instruction Code States T Bit 0 → M/Q/T DIV0U 0000000000011001 1 Description This instruction performs initial settings for unsigned division. This instruction is followed by a DIV1 instruction that executes 1-digit division, for example, and repeated divisions are executed to find the quotient.
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10.19 DIV1 DIVide 1 step Arithmetic Instruction Division Execution Format Summary of Operation Instruction Code States T Bit DIV1 Rm,Rn 1-step division 0011nnnnmmmm0100 1 Result of (Rn ÷ Rm) calculation Description This instruction performs 1-digit division (1-step division) of the 32-bit contents of general register Rn (dividend) by the contents of Rm (divisor).
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switch(old_q){ case 0:switch(M){ case 0:tmp0=R[n]; R[n]-=tmp2; tmp1=(R[n]>tmp0); switch(Q){ case 0:Q=tmp1; break; case 1:Q=(unsigned char)(tmp1==0); break; break; case 1:tmp0=R[n]; R[n]+=tmp2; tmp1=(R[n]<tmp0); switch(Q){ case 0:Q=(unsigned char)(tmp1==0); break; case 1:Q=tmp1; break; break; break; case 1:switch(M){ case 0:tmp0=R[n]; R[n]+=tmp2; tmp1=(R[n]<tmp0); switch(Q){ case 0:Q=tmp1; break; case 1:Q=(unsigned char)(tmp1==0);...
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R[n]-=tmp2; tmp1=(R[n]>tmp0); switch(Q){ case 0:Q=(unsigned char)(tmp1==0); break; case 1:Q=tmp1; break; break; break; T=(Q==M); PC+=2; Example 1 ;R1 (32 bits) ÷ R0 (16 bits) = R1 (16 bits); unsigned ;Set divisor in upper 16 bits, clear lower 16 bits to 0 SHLL16 ;Check for division by zero R0,R0...
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Example 2 ; R1:R2 (64 bits) ÷ R0 (32 bits) = R2 (32 bits); unsigned ;Check for division by zero R0,R0 ZERO_DIV ;Check for overflow CMP/HS R0,R1 OVER_DIV ;Flag initialization DIV0U .arepeat ;Repeat 32 times ROTCL DIV1 R0,R1 .aendr ;R2 = quotient ROTCL Example 3 ;R1 (16 bits) ÷...
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Example 4 ;R2 (32 bits) ÷ R0 (32 bits) = R2 (32 bits); signed R2,R3 ROTCL ;Dividend sign-extended to 64 bits (R1:R2) SUBC R1,R1 ;R3 = 0 R3,R3 ;If dividend is negative, subtract 1 to convert to one’s complement notation SUBC R3,R2 ;Flag initialization...
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10.20 DMULS.L Double-length MULtiply as Signed Arithmetic Instruction Signed Double-Length Multiplication Execution Format Summary of Operation Instruction Code States T Bit DMULS.L Rm,Rn Signed, 0011nnnnmmmm1101 2–5 — Rn × Rm → MACH, MACL Description This instruction performs 32-bit multiplication of the contents of general register Rn by the contents of Rm, and stores the 64-bit result in the MACH and MACL registers.
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temp0=RmL*RnL; temp1=RmH*RnL; temp2=RmL*RnH; temp3=RmH*RnH; Res2=0; Res1=temp1+temp2; if (Res1<temp1) Res2+=0x00010000; temp1=(Res1<<16)&0xFFFF0000; Res0=temp0+temp1; if (Res0<temp0) Res2++; Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3; if (fnLmL<0) { Res2= Res2; if (Res0==0) Res2++; else Res0=( Res0)+1; MACH=Res2; MACL=Res0; PC+=2; Example ;Before execution R0 = H’FFFFFFFE, R1 = H’00005555 DMULS.L R0,R1 ;After execution MACH = H’FFFFFFFF, MACL = H’FFFF5556 ;Get operation result (upper)
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10.21 DMULU.L Double-length MULtiply as Unsigned Arithmetic Instruction Unsigned Double-Length Multiplication Execution Format Summary of Operation Instruction Code States T Bit DMULU.L Rm,Rn Unsigned, 0011nnnnmmmm0101 2–5 — Rn × Rm → MACH, MACL Description This instruction performs 32-bit multiplication of the contents of general register Rn by the contents of Rm, and stores the 64-bit result in the MACH and MACL registers.
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Res0=temp0+temp1; if (Res0<temp0) Res2++; Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3; MACH=Res2; MACL=Res0; PC+=2; Example ;Before execution R0 = H’FFFFFFFE, R1 = H’00005555 DMULU.L R0,R1 ;After execution MACH = H’00005554, MACL = H’FFFF5556 ;Get operation result (upper) MACH,R0 ;Get operation result (lower) MACL,R1 Rev. 2.0, 03/99, page 239 of 396...
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10.22 Decrement and Test Arithmetic Instruction Decrement and Test Execution Format Summary of Operation Instruction Code States T Bit Rn – 1 → Rn; DT Rn 0100nnnn00010000 1 Test if Rn = 0, 1 → T result if Rn ≠ 0, 0 → T Description This instruction decrements the contents of general register Rn by 1 and compares the result with zero.
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10.23 EXTS EXTend as Signed Arithmetic Instruction Sign Extension Execution Format Summary of Operation Instruction Code States T Bit EXTS.B Rm,Rn Rm sign-extended from 0110nnnnmmmm1110 1 — byte → Rn EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 1 — word → Rn Description This instruction sign-extends the contents of general register Rm and stores the result in Rn.
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Example ;Before execution R0 = H’00000080 EXTS.B R0,R1 ;After execution R1 = H’FFFFFF80 ;Before execution R0 = H’00008000 EXTS.W R0,R1 ;After execution R1 = H’FFFF8000 Rev. 2.0, 03/99, page 242 of 396...
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10.24 EXTU EXTend as Unsigned Arithmetic Instruction Zero Extension Execution Format Summary of Operation Instruction Code States T Bit EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 1 — byte → Rn EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 1 — word → Rn Description This instruction zero-extends the contents of general register Rm and stores the result in Rn.
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10.25 FABS Floating-point ABSolute value Floating-Point Instruction Floating-Point Absolute Value Execution Format Summary of Operation Instruction Code States T Bit |FRn| → FRn FABS FRn 1111nnnn01011101 1 — |DRn| → DRn FABS DRn 1111nnn001011101 1 — Description This instruction clears the most significant bit of the contents of floating-point register FRn/DRn to 0, and stores the result in FRn/DRn.
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10.26 FADD Floating-point ADD Floating-Point Instruction Floating-Point Addition Execution Format Summary of Operation Instruction Code States T Bit FADD FRm,FRn FRn+FRm → FRn 1111nnnnmmmm0000 1 — FADD DRm,DRn DRn+DRm → DRn 1111nnn0mmm00000 6 — Description When FPSCR.PR = 0: Arithmetically adds the two single-precision floating-point numbers in FRn and FRm, and stores the result in FRn.
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case PZERO: switch (data_type_of(n)){ case NZERO: zero(n,0); break; default: break; break; case NZERO: break; case PINF: switch (data_type_of(n)){ case NINF: invalid(n); break; default: inf(n,0); break; break; case NINF: switch (data_type_of(n)){ case PINF: invalid(n); break; default: inf(n,1); break; break; FADD Special Cases FRm,DRm FRn,DRn NORM...
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10.27 FCMP Floating-point CoMPare Floating-Point Instruction Floating-Point Comparison Execution Format Summary of Operation Instruction Code States T Bit 1. FCMP/EQ FRm,FRn (FRn==FRm)?1:0 → T 1111nnnnmmmm0100 1 2. FCMP/EQ DRm,DRn (DRn==DRm)?1:0 → T 1111nnn0mmm00100 1 3. FCMP/GT FRm,FRn (FRn>FRm)?1:0 → T 1111nnnnmmmm0101 2 4.
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else T = 0; int fcmp_chk (int m,n) if((data_type_of(m) == sNaN) || (data_type_of(n) == sNaN)) return(INVALID); else if((data_type_of(m) == qNaN) || (data_type_of(n) == qNaN)) return(UO); else switch(data_type_of(m)){ case NORM: switch(data_type_of(n)){ case PINF :return(GT); break; case NINF :return(LT); break; default: break; break;...
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else return(LT); void fcmp_invalid() set_V(); if((FPSCR & ENABLE_V) == 0) T = 0; else fpu_exception_trap(); FCMP Special Cases FCMP/EQ FRn,DRn FRm,DRm NORM DNORM –0 +INF –INF qNaN sNaN NORM DNORM –0 +INF –INF qNaN sNaN Invalid Note: When DN = 1, the value of a denormalized number is treated as 0. FCMP/GT FRn,DRn FRm,DRm...
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10.28 FCNVDS Floating-point CoNVert Double to Single precision Floating-Point Instruction Double-Precision to Single-Precision Conversion Execution Format Summary of Operation Instruction Code States T Bit — — — — — (float)DRm → FPUL FCNVDS DRm,FPUL 1111mmm010111101 2 — Description When FPSCR.PR = 1: This instruction converts the double-precision floating-point number in DRm to a single-precision floating-point number, and stores the result in FPUL.
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qNaN *FPUL = 0x7fbfffff; break; sNaN set_V(); if((FPSCR & ENABLE_V) == 0) *FPUL = 0x7fbfffff; else fpu_exception_trap(); break; void normal_fcnvds(int m, float *FPUL) int sign; float abs; union { float f; int l; dstf,tmpf; union { double d; int l[2]; dstd;...
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10.29 FCNVSD Floating-point CoNVert Single to Double precision Floating-Point Instruction Single-Precision to Double-Precision Conversion Execution Format Summary of Operation Instruction Code States T Bit — — — — — (double) FPUL → DRn FCNVSD FPUL, DRn 1111nnn010101101 2 — Description When FPSCR.PR = 1: This instruction converts the single-precision floating-point number in FPUL to a double-precision floating-point number, and stores the result in DRn.
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int abs; abs = *FPUL & 0x7fffffff; if(abs < 0x00800000){ if((FPSCR_DN == 1) || (abs == 0x00000000)){ if(sign_of(src) == 0) return(PZERO); else return(NZERO); else return(DENORM); else if(abs < 0x7f800000) return(NORM); else if(abs == 0x7f800000) { if(sign_of(src) == 0) return(PINF); else return(NINF);...
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10.30 FDIV Floating-point DIVide Floating-Point Instruction Floating-Point Division Execution Format Summary of Operation Instruction Code States T Bit FRn/FRm → FRn FDIV FRm,FRn 1111nnnnmmmm0011 10 — DRn/DRm → DRn FDIV DRm,DRn 1111nnn0mmm00011 23 — Description When FPSCR.PR = 0: Arithmetically divides the single-precision floating-point number in FRn by the single-precision floating-point number in FRm, and stores the result in FRn.
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case PZERO: switch (data_type_of(n)){ case PZERO: case NZERO: invalid(n);break; case PINF: case NINF: break; default: dz(n,sign_of(m)^sign_of(n));break; break; case NZERO: switch (data_type_of(n)){ case PZERO: case NZERO: invalid(n); break; case PINF: inf(n,1); break; case NINF: inf(n,0); break; default: dz(FR[n],sign_of(m)^sign_of(n)); break; break; case DENORM: set_E();...
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tmpx; if(FPSCR_PR == 0) { tmpf.f = FR[n]; /* save destination value */ dstf.f /= FR[m]; /* round toward nearest or even */ tmpd.d = dstf.f; /* convert single to double */ tmpd.d *= FR[m]; if(tmpf.f != tmpd.d) set_I(); if((tmpf.f < tmpd.d) && (SPSCR_RM == 1)) dstf.l -= 1;...
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Possible Exceptions: • FPU error • Invalid operation • Divide by zero • Overflow • Underflow • Inexact Rev. 2.0, 03/99, page 257 of 396...
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10.31 FIPR Floating-point Inner PRoduct Floating-Point Instruction Floating-Point Inner Product Execution Format Summary of Operation Instruction Code States T Bit FVn ⋅ FVm → FR[n+3] FIPR FVm,FVn 1111nnmm11101101 1 — — — — — — — Notes: FV0 = {FR0, FR1, FR2, FR3} FV4 = {FR4, FR5, FR6, FR7} FV8 = {FR8, FR9, FR10, FR11} FV12 = {FR12, FR13, FR14, FR15}...
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When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not an exception has occurred. When an exception occurs, correct exception information is reflected in FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should therefore be performed by software.
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10.32 FLDI0 Floating-point LoaD Immediate 0.0 Floating-Point Instruction 0.0 Load Execution Format Summary of Operation Instruction Code States T Bit 0x00000000 → FRn FLDI0 FRn 1111nnnn10001101 1 — — — — — — Description When FPSCR.PR = 0, this instruction loads floating-point 0.0 (0x00000000) into FRn. Operation void FLDI0(int n) FR[n] = 0x00000000;...
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10.33 FLDI1 Floating-point LoaD Immediate 1.0 Floating-Point Instruction 1.0 Load Execution Format Summary of Operation Instruction Code States T Bit 0x3F800000 → FRn FLDI1 FRn 1111nnnn10011101 1 — — — — — — Description When FPSCR.PR = 0, this instruction loads floating-point 1.0 (0x3F800000) into FRn. Operation void FLDI1(int n) FR[n] = 0x3F800000;...
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10.34 FLDS Floating-point LoaD to System register Floating-Point Instruction Transfer to System Register Execution Format Summary of Operation Instruction Code States T Bit FRm → FPUL FLDS FRm,FPUL 1111mmmm00011101 1 — Description This instruction loads the contents of floating-point register FRm into system register FPUL. Operation void FLDS(int m, float *FPUL) *FPUL = FR[m];...
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10.35 FLOAT Floating-point convert from integer Floating-Point Instruction Integer to Floating-Point Conversion Execution Format Summary of Operation Instruction Code States T Bit (float)FPUL → FRn FLOAT FPUL,FRn 1111nnnn00101101 1 — (double)FPUL → DRn FLOAT FPUL,DRn 1111nnn000101101 2 — Description When FPSCR.PR = 0: Taking the contents of FPUL as a 32-bit integer, converts this integer to a single-precision floating-point number and stores the result in FRn.
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Operation void FLOAT(int n, float *FPUL) union { double d; int l[2]; tmp; pc += 2; clear_cause(); if(FPSCR.PR==0){ FR[n] = *FPUL; /* convert from integer to float */ tmp.d = *FPUL; if(tmp.l[1] & 0x1fffffff) inexact(); }else { DR[n>>1] = *FPUL; /* convert from integer to double */ Possible Exceptions: Inexact: Not generated when FPSCR.PR = 1.
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10.36 FMAC Floating-point Multiply and ACcumulate Floating-Point Instruction Floating-Point Multiply and Accumulate Execution PR Format Summary of Operation Instruction Code States T Bit FMAC FR0,FRm,FRn FR0*FRm+FRn → FRn 1111nnnnmmmm1110 1 — — — — — — Description When FPSCR.PR = 0: This instruction arithmetically multiplies the two single-precision floating- point numbers in FR0 and FRm, arithmetically adds the contents of FRn, and stores the result in FRn.
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case qNaN: qnan(n); break; case PZERO: case NZERO: zero(n,sign_of(0)^ sign_of(m)^sign_of(n)); break; default: break; case PINF: case NINF: switch (data_type_of(n)){ case DENORM: set_E(); break; case qNaN: qnan(n); break; case PINF: case NINF: if(sign_of(0)^ sign_of(m)^sign_of(n)) invalid(n); else inf(n,sign_of(0)^ sign_of(m)); break; default: inf(n,sign_of(0)^ sign_of(m)); break; case NORM: switch (data_type_of(n)){ case DENORM: set_E();...
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case PINF : case NINF : switch (data_type_of(m)){ case PZERO: case NZERO:invalid(n); break; default: switch (data_type_of(n)){ case DENORM: set_E(); break; case qNaN: qnan(n); break; default: inf(n,sign_of(0)^sign_of(m)^sign_of(n));break break; break; void normal_fmac(int m,n) union { int double x; int l[4]; dstx,tmpx; float dstf,srcf; if((data_type_of(n) == PZERO)|| (data_type_of(n) == NZERO)) srcf = 0.0;...
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if(FPSCR_RM == 1) { dstx.l[1] &= 0xfe000000; /* round toward zero */ dstx.l[2] = 0x00000000; dstx.l[3] = 0x00000000; dstf = dstx.x; check_single_exception(&FR[n],dstf); Rev. 2.0, 03/99, page 268 of 396...
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FMAC Special Cases +Norm -Norm –0 +INF –INF Denorm qNaN sNaN Norm Norm Invalid Invalid Norm Invalid Invalid –0 +Norm –0 +INF –INF –Norm –0 –INF +INF –0 –0 Invalid –0 –0 –0 Invalid +INF +Norm +INF Invalid –Norm +INF Invalid +INF Invalid...
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Possible Exceptions: • FPU error • Invalid operation • Overflow • Underflow • Inexact Rev. 2.0, 03/99, page 270 of 396...
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10.37 FMOV Floating-point MOVe Floating-Point Instruction Floating-Point Transfer Summary of Execution SZ Format Operation Instruction Code States T Bit FRm → FRn 1. FMOV FRm,FRn 1111nnnnmmmm1100 1 — DRm → DRn 2. FMOV DRm,DRn 1111nnn0mmm01100 1 — FRm → (Rn) 3.
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12. This instruction transfers contents of memory at address indicated by (R0 + Rm) to DRn. 13. This instruction transfers FRm contents to memory at address indicated by (R0 + Rn). 14. This instruction transfers DRm contents to memory at address indicated by (R0 + Rn). Operation void FMOV(int m,n) /* FMOV FRm,FRn */...
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load_int(R[m],FR[n]); R[m] += 4; pc += 2; void FMOV_RESTORE_DR(int m,n) /* FMOV @Rm+,DRn */ load_quad(R[m],DR[n>>1]) ; R[m] += 8; pc += 2; void FMOV_SAVE(int m,n) /* FMOV.S FRm,@–Rn */ store_int(FR[m],R[n]-4); R[n] -= 4; pc += 2; void FMOV_SAVE_DR(int m,n) /* FMOV DRm,@–Rn */ store_quad(DR[m>>1],R[n]-8);...
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void FMOV_INDEX_STORE_DR(int m,n)/*FMOV DRm,@(R0,Rn)*/ store_quad(DR[m>>1], R[0] + R[n]); pc += 2; Possible Exceptions: • Data TLB miss exception • Data protection violation exception • Initial write exception • Address error Rev. 2.0, 03/99, page 274 of 396...
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10.38 FMOV Floating-point MOVe extension Floating-Point Instruction Floating-Point Transfer Summary of Execution Format Operation Instruction Code States T Bit XRm → (Rn) 1. FMOV XDm,@Rn 1111nnnnmmm11010 1 — (Rm) → XDn 2. FMOV @Rm,XDn 1111nnn1mmmm1000 1 — (Rm) → XDn,Rm+=8 1111nnn1mmmm1001 1 3.
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Operation void FMOV_STORE_XD(int m,n) /* FMOV XDm,@Rn */ store_quad(XD[m>>1],R[n]); pc += 2; void FMOV_LOAD_XD(int m,n) /* FMOV @Rm,XDn */ load_quad(R[m],XD[n>>1]); pc += 2; void FMOV_RESTORE_XD(int m,n) /* FMOV @Rm+,DBn */ load_quad(R[m],XD[n>>1]); R[m] += 8; pc += 2; void FMOV_SAVE_XD(int m,n) /* FMOV XDm,@–Rn */ store_quad(XD[m>>1],R[n]-8);...
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void FMOV_XDDR(int m,n) /* FMOV XDm,DRn */ DR[n>>1] = XD[m>>1]; pc += 2; void FMOV_DRXD(int m,n) /* FMOV DRm,XDn */ XD[n>>1] = DR[m>>1]; pc += 2; Possible Exceptions: • Data TLB miss exception • Data protection violation exception • Initial write exception •...
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10.39 FMUL Floating-point MULtiply Floating-Point Instruction Floating-Point Multiplication Execution Format Summary of Operation Instruction Code States T Bit FRn*FRm → FRn FMUL FRm,FRn 1111nnnnmmmm0010 1 — DRn*DRm → DRn FMUL DRm,DRn 1111nnn0mmm00010 6 — Description When FPSCR.PR = 0: Arithmetically multiplies the two single-precision floating-point numbers in FRn and FRm, and stores the result in FRn.
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break; case PZERO: case NZERO: switch (data_type_of(n)){ case PINF: case NINF: invalid(n); break; default: zero(n,sign_of(m)^sign_of(n));break; break; case PINF : case NINF : switch (data_type_of(n)){ case PZERO: case NZERO: invalid(n); break; default: inf(n,sign_of(m)^sign_of(n));break break; FMUL Special Cases FRm,DRm FRn,DRn NORM –0 +INF –INF DENORM...
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10.40 FNEG Floating-point NEGate value Floating-Point Instruction Floating-Point Sign Inversion Execution Format Summary of Operation Instruction Code States T Bit -FRn → FRn FNEG FRn 1111nnnn01001101 1 — -DRn → DRn FNEG DRn 1111nnn001001101 1 — Description This instruction inverts the most significant bit (sign bit) of the contents of floating-point register FRn/DRn, and stores the result in FRn/DRn.
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10.41 FRCHG FR-bit CHanGe Floating-Point Instruction FR Bit Inversion Execution Format Summary of Operation Instruction Code States T Bit FRCHG FRSCR.FR=~FRSCR.FR 1111101111111101 1 — — — — — — Description This instruction inverts the FR bit in floating-point register FPSCR. When the FR bit in FPSCR is changed, FR0 to FR15 in FPPR0 to FPPR31 become XR0 to XR15, and XR0 to XR15 become FR0 to FR15.
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10.42 FSCHG Sz-bit CHanGe Floating-Point Instruction SZ Bit Inversion Execution Format Summary of Operation Instruction Code States T Bit FSCHG FRSCR.SZ=~FRSCR.SZ 1111001111111101 1 — — — — — — Description This instruction inverts the SZ bit in floating-point register FPSCR. Changing the SZ bit in FPSCR switches FMOV instruction data transfer between one single-precision data unit and a data pair.
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10.43 FSQRT Floating-point SQuare RooT Floating-Point Instruction Floating-Point Square Root Execution Format Summary of Operation Instruction Code States T Bit √FRn → FRn FSQRT FRn 1111nnnn01101101 9 — √DRn → DRn FSQRT DRn 1111nnnn01101101 22 — Description When FPSCR.PR = 0: Finds the arithmetical square root of the single-precision floating-point number in FRn, and stores the result in FRn.
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union { float f; int l; dstf,tmpf; union { double d; int l[2]; dstd,tmpd; union { int double x; int l[4]; tmpx; if(FPSCR_PR == 0) { tmpf.f = FR[n]; /* save destination value */ dstf.f = sqrt(FR[n]); /* round toward nearest or even */ tmpd.d = dstf.f;...
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FSQRT Special Cases +NORM –NORM –0 +INF –INF qNaN sNaN FSQRT(FRn) SQRT Invalid –0 +INF Invalid qNaN Invalid Note: When DN = 1, the value of a denormalized number is treated as 0. Possible Exceptions: • FPU error • Invalid operation •...
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10.44 FSTS Floating-point STore System register Floating-Point Instruction Transfer from System Register Execution Format Summary of Operation Instruction Code States T Bit FPUL → FRn FSTS FPUL,FRn 1111nnnn00001101 1 — Description This instruction transfers the contents of system register FPUL to floating-point register FRn. Operation void FSTS(int n, float *FPUL) FR[n] = *FPUL;...
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10.45 FSUB Floating-point SUBtract Floating-Point Instruction Floating-Point Subtraction Execution Format Summary of Operation Instruction Code States T Bit FRn-FRm → FRn FSUB FRm,FRn 1111nnnnmmmm0001 1 — FSUB DRm,DRn DRn-DRm → DRn 1111nnn0mmm00001 6 Description When FPSCR.PR = 0: Arithmetically subtracts the single-precision floating-point number in FRm from the single-precision floating-point number in FRn, and stores the result in FRn.
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break; case PZERO: break; case NZERO: switch (data_type_of(n)){ case NZERO: zero(n,0); break; default: break; break; case PINF: switch (data_type_of(n)){ case PINF: invalid(n); break; default: inf(n,1); break; break; case NINF: switch (data_type_of(n)){ case NINF: invalid(n); break; default: inf(n,0); break; break; FSUB Special Cases FRm,DRm FRn,DRn NORM...
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10.46 FTRC Floating-point TRuncate and Convert to integer Floating-Point Instruction Conversion to Integer Execution Format Summary of Operation Instruction Code States T Bit (long)FRm → FPUL FTRC FRm,FPUL 1111mmmm00111101 1 — (long)DRm → FPUL FTRC DRm,FPUL 1111mmm000111101 2 — Description When FPSCR.PR = 0: Converts the single-precision floating-point number in FRm to a 32-bit integer, and stores the result in FPUL.
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NORM: *FPUL = DR[m>>1]; break; PINF: ftrc_invalid(0); break; NINF: ftrc_invalid(1); break; int ftrc_signle_type_of(int m) if(sign_of(m) == 0){ if(FR_HEX[m] > 0x7f800000) return(NINF); /* NaN */ else if(FR_HEX[m] > P_INT_SINGLE_RANGE) return(PINF); /* out of range,+INF */ else return(NORM); /* +0,+NORM }else { if((FR_HEX[m] &...
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if((FPSCR & ENABLE_V) == 0){ if(sign == 0) *FPUL = 0x7fffffff; else *FPUL = 0x80000000; else fpu_exception_trap(); FTRC Special Cases Positive Negative Out of Out of FRn,DRn NORM –0 Range Range +INF –INF qNaN sNaN FTRC Invalid Invalid Invalid Invalid Invalid Invalid (FRn,DRn)
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10.47 FTRV Floating-point TRansform Vector Floating-Point Instruction Vector Transformation Execution Format Summary of Operation Instruction Code States T Bit FTRV XMTRX,FVn XMTRX*FVn → FVn 1111nn0111111101 4 — — — — — — Description When FPSCR.PR = 0: This instruction takes the contents of floating-point registers XF0 to XF15 indicated by XMTRX as a 4-row ×...
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5. If the input values do not include an sNaN, qNaN, or infinity, processing is performed in the normal way. When FPSCR.enable.V/O/U/I is set, an FPU exception trap is generated regardless of whether or not an exception has occurred. When an exception occurs, correct exception information is reflected in FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated.
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Possible Exceptions: • Invalid operation • Overflow • Underflow • Inexact Rev. 2.0, 03/99, page 294 of 396...
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10.48 JuMP Branch Instruction Unconditional Branch Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit Rn → PC JMP @Rn 0100nnnn00101011 2 — Description Unconditionally makes a delayed branch to the address specified by Rn. Notes As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.
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10.49 Jump to SubRoutine Branch Instruction Branch to Subroutine Procedure Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit PC+4 → PR, Rn → PC JSR @Rn 0100nnnn00001011 2 — Description This instruction makes a delayed branch to the subroutine procedure at the specified address after execution of the following instruction.
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Example ;R0 = TRGET address MOV.L JSR_TABLE,R0 ;Branch to TRGET. ;XOR executed before branch. R1,R1 ;← Procedure return destination (PR contents) R0,R1 ..align ;Jump table JSR_TABLE: . data.l TRGET ;← Entry to procedure TRGET: R2,R3 ;Return to above ADD instruction. ;MOV executed before RTS.
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10.50 LoaD to Control register System Control Instruction Load to Control Register (Privileged Instruction) Execution Format Summary of Operation Instruction Code States T Bit Rm → SR Rm, SR 0100mmmm00001110 Rm → GBR Rm, GBR — 0100mmmm00011110 Rm → VBR Rm, VBR —...
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Notes With the exception of LDC Rm,GBR and LDC.L @Rm+,GBR, the LDC/LDC.L instructions are privileged instructions and can only be used in privileged mode. Use in user mode will cause an illegal instruction exception. However, LDC Rm,GBR and LDC.L @Rm+,GBR can also be used in user mode.
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PC+=2; LDCDBR(int m) /* LDC Rm,DBR : Privileged */ DBR=R[m]; PC+=2; LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */ /* n=0–7 */ Rn_BANK=R[m]; PC+=2; LDCMSR(int m) /* LDC.L @Rm+,SR : Privileged */ SR=Read_Long(R[m])&0x700083F3; R[m]+=4; PC+=2; LDCMGBR(int m) /* LDC.L @Rm+,GBR */ GBR=Read_Long(R[m]);...
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LDCMSSR(int m) /* LDC.L @Rm+,SSR : Privileged */ SSR=Read_Long(R[m]); R[m]+=4; PC+=2; LDCMSPC(int m) /* LDC.L @Rm+,SPC : Privileged */ SPC=Read_Long(R[m]); R[m]+=4; PC+=2; LDCMDBR(int m) /* LDC.L @Rm+,DBR : Privileged */ DBR=Read_Long(R[m]); R[m]+=4; PC+=2; LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */ /* n=0–7 */ Rn_BANK=Read_Long(R[m]);...
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10.51 LoaD to FPU System register System Control Instruction Load to FPU System Register Execution Format Summary of Operation Instruction Code States T Bit Rm → FPUL Rm,FPUL 0100mmmm01011010 1 — (Rm) → FPUL, Rm+4 → Rm LDS.L @Rm+,FPUL 0100mmmm01010110 1 —...
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R[m]+=4; PC+=2; Possible Exceptions: • Data TLB miss exception • Data access protection exception • Address error Rev. 2.0, 03/99, page 303 of 396...
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10.52 LoaD to System register System Control Instruction Load to System Register Execution Format Summary of Operation Instruction Code States T Bit Rm → MACH Rm,MACH 0100mmmm00001010 1 — Rm → MACL Rm,MACL 0100mmmm00011010 1 — Rm,PR Rm→ PR 0100mmmm00101010 2 —...
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MACH=Read_Long(R[m]); R[m]+=4; PC+=2; LDSMMACL(int m) /* LDS.L @Rm+,MACL */ MACL=Read_Long(R[m]); R[m]+=4; PC+=2; LDSMPR(int m) /* LDS.L @Rm+,PR */ PR=Read_Long(R[m]); R[m]+=4; PC+=2; Example ; Before execution R0 = H’12345678, PR = H’00000000 R0,PR ; After execution PR = H’12345678 ; Before execution R15 = H’10000000 LDS.L @R15+,MACL...
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10.53 LDTLB LoaD PTEH/PTEL/PTEA to TLB System Control Instruction Load to TLB (Privileged Instruction) Execution Format Summary of Operation Instruction Code States T Bit PTEH/PTEL/PTEA → TLB LDTLB 0000000000111000 1 — Description This instruction loads the contents of the PTEH/PTEL/PTEA registers into the TLB (translation lookaside buffer) specified by MMUCR.URC (random counter field in the MMC control register).
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Operation LDTLB( ) /*LDTLB */ TLB[MMUCR. URC] .ASID=PTEH & 0x000000FF; TLB[MMUCR. URC] .VPN=(PTEH & 0xFFFFFC00)>>10; TLB[MMUCR. URC] .PPN=(PTEH & 0x1FFFFC00)>>10; TLB[MMUCR. URC] .SZ=(PTEL & 0x00000080)>>6 | (PTEL & 0x00000010)>>4; TLB[MMUCR. URC] .SH=(PTEH & 0x00000002)>>1; TLB[MMUCR. URC] .PR=(PTEH & 0x00000060)>>5; TLB[MMUCR. URC] .WT=(PTEH & 0x00000001); TLB[MMUCR.
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10.54 MAC.L Multiply and ACcumulate Long Arithmetic Instruction Double-Precision Multiply-and-Accumulate Operation Execution Format Summary of Operation Instruction Code States T Bit MAC.L @Rm+,@Rn+ Signed, 0000nnnnmmmm1111 2–5 — (Rn) × (Rm) + MAC → MAC Rn + 4 → Rn, Rm + 4 → Rm Description This instruction performs signed multiplication of the 32-bit operands whose addresses are the contents of general registers Rm and Rn, adds the 64-bit result to the MAC register contents, and...
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if (tempn<0) tempn=0-tempn; if (tempm<0) tempm=0-tempm; temp1=(unsigned long)tempn; temp2=(unsigned long)tempm; RnL=temp1&0x0000FFFF; RnH=(temp1>>16)&0x0000FFFF; RmL=temp2&0x0000FFFF; RmH=(temp2>>16)&0x0000FFFF; temp0=RmL*RnL; temp1=RmH*RnL; temp2=RmL*RnH; temp3=RmH*RnH; Res2=0; Res1=temp1+temp2; if (Res1<temp1) Res2+=0x00010000; temp1=(Res1<<16)&0xFFFF0000; Res0=temp0+temp1; if (Res0<temp0) Res2++; Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3; if(fnLmL<0){ Res2= Res2; if (Res0==0) Res2++; else Res0=( Res0)+1; if(S==1){ Res0=MACL+Res0; if (MACL>Res0) Res2++;...
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Res2+=MACH&0x00007FFF; if(((long)Res2<0)&&(Res2<0xFFFF8000)){ Res2=0xFFFF8000; Res0=0x00000000; if(((long)Res2>0)&&(Res2>0x00007FFF)){ Res2=0x00007FFF; Res0=0xFFFFFFFF; MACH=(Res2&0x0000FFFF)|(MACH&0xFFFF0000); MACL=Res0; else { Res0=MACL+Res0; if (MACL>Res0) Res2++; Res2+=MACH; MACH=Res2; MACL=Res0; PC+=2; Rev. 2.0, 03/99, page 310 of 396...
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Example ;Get table address MOVA TBLM,R0 R0,R1 ;Get table address MOVA TBLN,R0 ;MAC register initialization CLRMAC MAC.L @R0+,@R1+ MAC.L @R0+,@R1+ ;Get result in R0 MACL,R0 ..align TBLM .data.l H’1234ABCD .data.l H’5678EF01 TBLN .data.l H’0123ABCD .data.l H’4567DEF0 Rev. 2.0, 03/99, page 311 of 396...
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10.55 MAC.W Multiply and ACcumulate Word Arithmetic Instruction Single-Precision Multiply-and-Accumulate Operation Execution Format Summary of Operation Instruction Code States T Bit MAC.W @Rm+,@Rn+ Signed, 0100nnnnmmmm1111 2–5 — (Rn) × (Rm) + MAC →MAC @Rm+,@Rn+ Rn + 2 → Rn, Rm + 2 → Rm Description This instruction performs signed multiplication of the 16-bit operands whose addresses are the contents of general registers Rm and Rn, adds the 32-bit result to the MAC register contents, and...
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Operation MACW(long m, long n) /* MAC.W @Rm+,@Rn+ */ long tempm,tempn,dest,src,ans; unsigned long templ; tempn=(long)Read_Word(R[n]); R[n]+=2; tempm=(long)Read_Word(R[m]); R[m]+=2; templ=MACL; tempm=((long)(short)tempn*(long)(short)tempm); if ((long)MACL>=0) dest=0; else dest=1; if ((long)tempm>=0) { src=0; tempn=0; else { src=1; tempn=0xFFFFFFFF; src+=dest; MACL+=tempm; if ((long)MACL>=0) ans=0; else ans=1; ans+=dest;...
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PC+=2; Example ;Get table address MOVA TBLM,R0 R0,R1 ;Get table address MOVA TBLN,R0 ;MAC register initialization CLRMAC MAC.W @R0+,@R1+ MAC.W @R0+,@R1+ ;Get result in R0 MACL,R0 ... .align 2 .data.w TBLM H’1234 .data.w H’5678 .data.w TBLN H’0123 .data.w H’4567 Rev. 2.0, 03/99, page 314 of 396...
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10.56 MOVe data Data Transfer Instruction Data Transfer Execution Format Summary of Operation Instruction Code States T Bit Rm → Rn Rm,Rn 0110nnnnmmmm0011 1 — Rm → (Rn) MOV.B Rm,@Rn 0010nnnnmmmm0000 1 — Rm → (Rn) MOV.W Rm,@Rn 0010nnnnmmmm0001 1 —...
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Operation MOV(long m, long n) /* MOV Rm,Rn */ R[n]=R[m]; PC+=2; MOVBS(long m, long n) /* MOV.B Rm,@Rn */ Write_Byte(R[n],R[m]); PC+=2; MOVWS(long m, long n) /* MOV.W Rm,@Rn */ Write_Word(R[n],R[m]); PC+=2; MOVLS(long m, long n) /* MOV.L Rm,@Rn */ Write_Long(R[n],R[m]); PC+=2;...
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else R[n]|=0xFFFF0000; PC+=2; MOVLL(long m, long n) /* MOV.L @Rm,Rn */ R[n]=Read_Long(R[m]); PC+=2; MOVBM(long m, long n) /* MOV.B Rm,@-Rn */ Write_Byte(R[n]-1,R[m]); R[n]-=1; PC+=2; MOVWM(long m, long n) /* MOV.W Rm,@-Rn */ Write_Word(R[n]-2,R[m]); R[n]-=2; PC+=2; MOVLM(long m, long n) /* MOV.L Rm,@-Rn */ Write_Long(R[n]-4,R[m]);...
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PC+=2; MOVWP(long m, long n) /* MOV.W @Rm+,Rn */ R[n]=(long)Read_Word(R[m]); if ((R[n]&0x8000)==0) R[n]&=0x0000FFFF; else R[n]|=0xFFFF0000; if (n!=m) R[m]+=2; PC+=2; MOVLP(long m, long n) /* MOV.L @Rm+,Rn */ R[n]=Read_Long(R[m]); if (n!=m) R[m]+=4; PC+=2; MOVBS0(long m, long n) /* MOV.B Rm,@(R0,Rn) */ Write_Byte(R[n]+R[0],R[m]);...
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R[n]=(long)Read_Byte(R[m]+R[0]); if ((R[n]&0x80)==0) R[n]&=0x000000FF; else R[n]|=0xFFFFFF00; PC+=2; MOVWL0(long m, long n) /* MOV.W @(R0,Rm),Rn */ R[n]=(long)Read_Word(R[m]+R[0]); if ((R[n]&0x8000)==0) R[n]&=0x0000FFFF; else R[n]|=0xFFFF0000; PC+=2; MOVLL0(long m, long n) /* MOV.L @(R0,Rm),Rn */ R[n]=Read_Long(R[m]+R[0]); PC+=2; Example ;Before execution R0 = H’FFFFFFFF, R1 = H’00000000 R0,R1 ;After execution R1 = H’FFFFFFFF...
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10.57 MOVe constant value Data Transfer Instruction Immediate Data Transfer Execution Format Summary of Operation Instruction Code States T Bit #imm,Rn imm sign extension Rn 1110nnnniiiiiiii 1 — MOV.W @(disp,PC),Rn (disp×2+PC+4) → sign 1001nnnndddddddd 1 — extension Rn MOV.L @(disp,PC),Rn (disp×4+PC+4) → Rn 1101nnnndddddddd 1 —...
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Operation MOVI(int i, int n) /* MOV #imm,Rn */ if ((i&0x80)==0) R[n]=(0x000000FF & i); else R[n]=(0xFFFFFF00 | i); PC+=2; MOVWI(d, n) /* MOV.W @(disp,PC),Rn */ unsigned int disp; disp=(unsigned int)(0x000000FF & d); R[n]=(int)Read_Word(PC+4+(disp<<1)); if ((R[n]&0x8000)==0) R[n]&=0x0000FFFF; else R[n]|=0xFFFF0000; PC+=2; MOVLI(int d, int n)/* MOV.L @(disp,PC),Rn */ unsigned int disp;...
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Example Address ;R1 = H’FFFFFF80 1000 #H’80,R1 ;R2 = H’FFFF9ABC IMM means (PC + 4 + H’08) 1002 MOV.W IMM,R2 1004 #-1,R0 1006 R0,R0 ;R3 = H’12345678 1008 MOV.L @(3,PC),R3 ;Delayed branch instruction 100A NEXT 100C 100E IMM .data.w H’9ABC 1010 .data.w H’1234...
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10.58 MOVe global data Data Transfer Instruction Global Data Transfer Execution Format Summary of Operation Instruction Code States T Bit (disp+GBR) → sign MOV.B @(disp,GBR),R0 11000100dddddddd 1 — extension R0 (disp×2+GBR) → sign MOV.W @(disp,GBR), R0 11000101dddddddd 1 — extension R0 (disp×4+GBR) →...
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Operation MOVBLG(int d) /* MOV.B @(disp,GBR),R0 */ unsigned int disp; disp=(unsigned int)(0x000000FF & d); R[0]=(int)Read_Byte(GBR+disp); if ((R[0]&0x80)==0) R[0]&=0x000000FF; else R[0]|=0xFFFFFF00; PC+=2; MOVWLG(int d) /* MOV.W @(disp,GBR),R0 */ unsigned int disp; disp=(unsigned int)(0x000000FF & d); R[0]=(int)Read_Word(GBR+(disp<<1)); if ((R[0]&0x8000)==0) R[0]&=0x0000FFFF; else R[0]|=0xFFFF0000; PC+=2;...
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disp=(unsigned int)(0x000000FF & d); Write_Byte(GBR+disp,R[0]); PC+=2; MOVWSG(int d) /* MOV.W R0,@(disp,GBR) */ unsigned int disp; disp=(unsigned int)(0x000000FF & d); Write_Word(GBR+(disp<<1),R[0]); PC+=2; MOVLSG(int d) /* MOV.L R0,@(disp,GBR) */ unsigned int disp; disp=(unsigned int)(0x000000FF & (long)d); Write_Long(GBR+(disp<<2),R[0]); PC+=2; Example ;Before execution (GBR+8) = H’12345670 MOV.L @(2,GBR),R0 ;After execution R0 = (H’12345670)
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10.59 MOVe structure data Data Transfer Instruction Structure Data Transfer Execution Format Summary of Operation Instruction Code States T Bit R0 → (disp+Rn) MOV.B R0,@(disp,Rn) 10000000nnnndddd 1 — R0 → (disp×2+Rn) MOV.W R0,@(disp,Rn) 10000001nnnndddd 1 — Rm → (disp×4+Rn) MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd 1 —...
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Operation MOVBS4(long d, long n /* MOV.B R0,@(disp,Rn) */ long disp; disp=(0x0000000F & (long)d); Write_Byte(R[n]+disp,R[0]); PC+=2; MOVWS4(long d, long n) /* MOV.W R0,@(disp,Rn) */ long disp; disp=(0x0000000F & (long)d); Write_Word(R[n]+(disp<<1),R[0]); PC+=2; MOVLS4(long m, long d, long n) /* MOV.L Rm,@(disp,Rn) */ long disp;...
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MOVWL4(long m, long d) /* MOV.W @(disp,Rm),R0 */ long disp; disp=(0x0000000F & (long)d); R[0]=Read_Word(R[m]+(disp<<1)); if ((R[0]&0x8000)==0) R[0]&=0x0000FFFF; else R[0]|=0xFFFF0000; PC+=2; MOVLL4(long m, long d, long n) /* MOV.L @(disp,Rm),Rn */ long disp; disp=(0x0000000F & (long)d); R[n]=Read_Long(R[m]+(disp<<2)); PC+=2; Example ;Before execution (R0+8) = H’12345670 MOV.L @(2,R0),R1 ;After execution...
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10.60 MOVA MOVe effective Address Data Transfer Instruction Effective Address Transfer Execution Format Summary of Operation Instruction Code States T Bit MOVA @(disp,PC),R0 disp×4+PC+4 → R0 11000111dddddddd 1 — Description This instruction stores the source operand effective address in general register R0. The 8-bit displacement is multiplied by four after zero-extension.
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10.61 MOVCA.L MOVe with Cache block Allocation Data Transfer Instruction Cache Block Allocation Execution Format Summary of Operation Instruction Code States T Bit R0 → (Rn) MOVCA.L R0,@Rn 0000nnnn11000011 1 — Description This instruction stores the contents of general register R0 in the memory location indicated by effective address Rn.
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10.62 MOVT MOVe T bit Data Transfer Instruction T Bit Transfer Execution Format Summary of Operation Instruction Code States T Bit T → Rn MOVT Rn 0000nnnn00101001 1 — Description This instruction stores the T bit in general register Rn. When T = 1, Rn = 1; when T = 0, Rn = 0. Operation MOVT(long n) /* MOVT Rn */...
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10.63 MUL.L MULtiply Long Arithmetic Instruction Double-Precision Multiplication Execution Format Summary of Operation Instruction Code States T Bit Rn×Rm → MACL MUL.L Rm,Rn 0000nnnnmmmm0111 2–5 — Description This instruction performs 32-bit multiplication of the contents of general registers Rn and Rm, and stores the lower 32 bits of the result in the MACL register.
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10.64 MULS.W MULtiply as Signed Word Arithmetic Instruction Signed Multiplication Execution Format Summary of Operation Instruction Code States T Bit Signed, Rn × Rm → MACL MULS.W Rm,Rn 0010nnnnmmmm1111 2–5 — MULS Rm,Rn Description This instruction performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-bit result in the MACL register.
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10.65 MULU.W MULtiply as Unsigned Word Arithmetic Instruction Unsigned Multiplication Execution Format Summary of Operation Instruction Code States T Bit Unsigned, Rn × Rm → MACL MULU.W Rm,Rn 0010nnnnmmmm1110 2–5 — MULU Rm,Rn Description This instruction performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-bit result in the MACL register.
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10.66 NEGate Arithmetic Instruction Sign Inversion Execution Format Summary of Operation Instruction Code States T Bit 0-Rm → Rn NEG Rm,Rn 0110nnnnmmmm1011 1 — Description This instruction finds the two’s complement of the contents of general register Rm and stores the result in Rn.
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10.67 NEGC NEGate with Carry Arithmetic Instruction Sign Inversion with Borrow Execution Format Summary of Operation Instruction Code States T Bit 0 – Rm – T → Rn, NEGC Rm,Rn 0110nnnnmmmm1010 1 Borrow borrow → T Description This instruction subtracts the contents of general register and the T bit from 0 and stores the result in Rn.
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10.68 No OPeration System Control Instruction No Operation Execution States Format Summary of Operation Instruction Code T Bit No operation 0000000000001001 1 — Description This instruction simply increments the program counter (PC), advancing the processing flow to execution of the next instruction. Operation NOP( ) /* NOP */ PC+=2;...
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10.69 NOT-logical complement Logical Instruction Bit Inversion Execution Format Summary of Operation Instruction Code States T Bit ∼Rm → Rn NOT Rm,Rn 0110nnnnmmmm0111 1 — Description This instruction finds the one’s complement of the contents of general register Rm and stores the result in Rn.
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10.70 OCBI Operand Cache Block Invalidate Data Transfer Instruction Cache Block Invalidation Execution Format Summary of Operation Instruction Code States T Bit OCBI @Rn Operand cache block 0000nnnn10010011 1 — invalidation Description This instruction accesses data using the contents indicated by effective address Rn. In the case of a hit in the cache, the corresponding cache block is invalidated (the V bit is cleared to 0).
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10.71 OCBP Operand Cache Block Purge Data Transfer Instruction Cache Block Purge Execution States Format Summary of Operation Instruction Code T Bit OCBP @Rn Operand cache block purge 0000nnnn10100011 1 — Description This instruction accesses data using the contents indicated by effective address Rn. If the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to external memory and that block is invalidated (the V bit is cleared to 0).
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10.72 OCBWB Operand Cache Block Write Back Data Transfer Instruction Cache Block Write-Back Execution Format Summary of Operation Instruction Code States T Bit OCBWB @Rn Operand cache block write- 0000nnnn10110011 1 — back Description This instruction accesses data using the contents indicated by effective address Rn. If the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to external memory and that block is cleaned (the U bit is cleared to 0).
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10.73 OR logical Logical Instruction Logical OR Execution Format Summary of Operation Instruction Code States T Bit Rn | Rm → Rn Rm,Rn 0010nnnnmmmm1011 1 — R0 | imm → R0 #imm,R0 11001011iiiiiiii 1 — (R0+GBR) | imm → OR.B #imm,@(R0,GBR) 11001111iiiiiiii 4 —...
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Operation OR(long m, long n) /* OR Rm,Rn */ R[n]|=R[m]; PC+=2; ORI(long i) /* OR #imm,R0 */ R[0]|=(0x000000FF & (long)i); PC+=2; ORM(long i) /* OR.B #imm,@(R0,GBR) */ long temp; temp=(long)Read_Byte(GBR+R[0]); temp|=(0x000000FF & (long)i); Write_Byte(GBR+R[0],temp); PC+=2; Example ;Before execution R0 = H’AAAA5555, R1 = H’55550000 R0,R1 ;After execution R1 = H’FFFF5555...
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10.74 PREF PREFetch data to cache Data Transfer Instruction Prefetch to Data Cache Execution Format Summary of Operation Instruction Code States T Bit PREF @Rn Prefetch cache block — 0000nnnn10000011 Description This instruction reads a 32-byte data block starting at a 32-byte boundary into the operand cache. The lower 5 bits of the address specified by Rn are masked to zero.
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10.75 ROTCL ROTate with Carry Left Shift Instruction One-Bit Left Rotation through T Bit Execution Format Summary of Operation Instruction Code States T Bit T ← Rn ← T ROTCL Rn 0100nnnn00100100 1 Description This instruction rotates the contents of general register Rn one bit to the left through the T bit, and stores the result in Rn.
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10.76 ROTCR ROTate with Carry Right Shift Instruction One-Bit Right Rotation through T Bit Execution Format Summary of Operation Instruction Code States T Bit T → Rn → T ROTCR Rn 0100nnnn00100101 1 Description This instruction rotates the contents of general register Rn one bit to the right through the T bit, and stores the result in Rn.
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10.77 ROTL ROTate Left Shift Instruction One-Bit Left Rotation Execution Format Summary of Operation Instruction Code States T Bit T ← Rn ← MSB ROTL Rn 0100nnnn00000100 1 Description This instruction rotates the contents of general register Rn one bit to the left, and stores the result in Rn.
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10.78 ROTR ROTate Right Shift Instruction One-Bit Right Rotation Execution Format Summary of Operation Instruction Code States T Bit LSB → Rn → T ROTR 0100nnnn00000101 1 Description This instruction rotates the contents of general register Rn one bit to the right, and stores the result in Rn.
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10.79 ReTurn from Exception System Control Instruction Return from Exception Handling (Privileged Instruction) Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit SSR → SR, SPC→ PC 0000000000101011 5 — Description This instruction returns from an exception or interrupt handling routine by restoring the PC and SR values from SPC and SSR.
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Operation RTE( ) /* RTE */ unsigned int temp; temp=PC; SR=SSR; PC=SPC; Delay_Slot(temp+2); Example ;Return to original routine. ;Executed before branch. #8,R14 Note: In a delayed branch, the actual branch operation occurs after execution of the slot instruction, but instruction execution (register updating, etc.) is in fact performed in delayed branch instruction →...
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10.80 ReTurn from Subroutine Branch Instruction Return from Subroutine Procedure Delayed Branch Instruction Execution Format Summary of Operation Instruction Code States T Bit PR → PC 0000000000001011 2 — Description This instruction returns from a subroutine procedure by restoring the PC from PR. Processing continues from the address indicated by the restored PC value.
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Example ;R3 = TRGET address MOV.L TABLE,R3 ; Branch to TRGET. ;NOP executed before branch. ;← Subroutine procedure return destination (PR contents) R0,R1 ..;Jump table TABLE: .data.l TRGET ..;← Entry to procedure TRGET: R1,R0 ;PR contents → PC ;MOV executed before branch.
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10.81 SETS SET S bit System Control Instruction S Bit Setting Execution Format Summary of Operation Instruction Code States T Bit 1 → S SETS 0000000001011000 1 — Description This instruction sets the S bit to 1. Operation SETS( ) /* SETS */ S=1;...
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10.82 SETT SET T bit System Control Instruction T Bit Setting Execution Format Summary of Operation Instruction Code States T Bit 1 → T SETT 0000000000011000 1 Description This instruction sets the T bit to 1. Operation SETT( ) /* SETT */ T=1;...
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10.83 SHAD SHift Arithmetic Dynamically Shift Instruction Dynamic Arithmetic Shift Execution Format Summary of Operation Instruction Code States T Bit When Rm ≥ 0, SHAD Rm, Rn 0100nnnnmmmm1100 1 — Rn << Rm → Rn When Rm < 0, Rn >> Rm → [MSB → Rn] Description This instruction arithmetically shifts the contents of general register Rn.
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Operation SHAD(int m,n) /*SHAD Rm,Rn */ int sgn=R[m] & 0x80000000; if (sgn==0) R[n] <<= (R[m] & 0x1F); else if ((R[m] & 0x1F) == 0) { if ((R[n] & 0x80000000) == 0) R[n] = 0; else R[n] = 0xFFFFFFFF; else R[n]=(long)R[n] >> ((~R[m] & 0x1F)+1); PC+=2;...
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10.84 SHAL SHift Arithmetic Left Shift Instruction One-Bit Left Arithmetic Shift Execution Format Summary of Operation Instruction Code States T Bit T ← Rn ← 0 SHAL Rn 0100nnnn00100000 1 Description This instruction arithmetically shifts the contents of general register Rn one bit to the left, and stores the result in Rn.
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10.85 SHAR SHift Arithmetic Right Shift Instruction One-Bit Right Arithmetic Shift Execution Format Summary of Operation Instruction Code States T Bit MSB → Rn → T SHAR 0100nnnn00100001 1 Description This instruction arithmetically shifts the contents of general register Rn one bit to the right, and stores the result in Rn.
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10.86 SHLD SHift Logical Dynamically Shift Instruction Dynamic Logical Shift Execution Format Summary of Operation Instruction Code States T Bit When Rm ≥ 0, SHLD Rm, Rn 0100nnnnmmmm1101 1 — Rn << Rm → Rn When Rm < 0, Rn >> Rm → [0 → Rn] Description This instruction logically shifts the contents of general register Rn.
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Operation SHLD(int m,n)/*SHLD Rm,Rn */ int sgn = R[m] & 0x80000000; if (sgn == 0) R[n] <<= (R[m] & 0x1F); else if ((R[m] & 0x1F) == 0) R[n] = 0; else R[n]=(unsigned)R[n] >> ((~R[m] & 0x1F)+1); PC+=2; Example ;Before execution R1 = H’FFFFFFEC, R2 = H’80180000 SHLD R1, R2 ;After execution...
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10.87 SHLL SHift Logical Left Shift Instruction One-Bit Left Logical Shift Execution Format Summary of Operation Instruction Code States T Bit T ← Rn ← 0 SHLL Rn 0100nnnn00000000 1 Description This instruction logically shifts the contents of general register Rn one bit to the left, and stores the result in Rn.
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10.88 SHLLn n bits SHift Logical Left Shift Instruction n-Bit Left Logical Shift Execution Format Summary of Operation Instruction Code States T Bit Rn<<2 → Rn SHLL2 0100nnnn00001000 1 — Rn<<8 → Rn SHLL8 0100nnnn00011000 1 — Rn<<16 → Rn SHLL16 Rn 0100nnnn00101000 1 —...
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Operation SHLL2(long n) /* SHLL2 Rn */ R[n]<<=2; PC+=2; SHLL8(long n) /* SHLL8 Rn */ R[n]<<=8; PC+=2; SHLL16(long n) /* SHLL16 Rn */ R[n]<<=16; PC+=2; Example ;Before execution R0 = H’12345678 SHLL2 ;After execution R0 = H’48D159E0 ;Before execution R0 = H’12345678 SHLL8 ;After execution R0 = H’34567800...
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10.89 SHLR SHift Logical Right Shift Instruction One-Bit Right Logical Shift Execution Format Summary of Operation Instruction Code States T Bit 0 → Rn → T SHLR 0100nnnn00000001 1 Description This instruction logically shifts the contents of general register Rn one bit to the right, and stores the result in Rn.
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10.90 SHLRn n bits SHift Logical Right Shift Instruction n-Bit Right Logical Shift Execution Format Summary of Operation Instruction Code States T Bit Rn>>2 → Rn SHLR2 0100nnnn00001001 1 — Rn>>8 → Rn SHLR8 0100nnnn00011001 1 — Rn>>16 → Rn SHLR16 Rn 0100nnnn00101001 1 —...
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Operation SHLR2(long n) /* SHLR2 Rn */ R[n]>>=2; R[n]&=0x3FFFFFFF; PC+=2; SHLR8(long n) /* SHLR8 Rn */ R[n]>>=8; R[n]&=0x00FFFFFF; PC+=2; SHLR16(long n) /* SHLR16 Rn */ R[n]>>=16; R[n]&=0x0000FFFF; PC+=2; Example ;Before execution R0 = H’12345678 SHLR2 ;After execution R0 = H’048D159E ;Before execution R0 = H’12345678 SHLR8 ;After execution...
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10.91 SLEEP SLEEP System Control Instruction Transition to Power-Down Mode (Privileged Instruction) Execution Format Summary of Operation Instruction Code States T Bit SLEEP Sleep 0000000000011011 4 — Description This instruction places the CPU in the power-down state. In power-down mode, the CPU retains its internal state, but immediately stops executing instructions and waits for an interrupt request.
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10.92 STore Control register System Control Instruction Store from Control Register (Privileged Instruction) Execution Format Summary of Operation Instruction Code States T Bit SR → Rn SR, Rn — 0000nnnn00000010 GBR → Rn GBR, Rn — 0000nnnn00010010 VBR → Rn VBR, Rn —...
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Description This instruction stores control register SR, GBR, VBR, SSR, SPC, SGR, DBR or Rm_BANK (m = 0–7) in the destination. Rm_BANK operands are specified by the RB bit of the SR register: when the RB bit is 1 Rm_BANK0 is accessed, when the RB bit is 0 Rm_BANK1 is accessed.
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STCSPC(int n) /* STC SPC,Rn : Privileged */ R[n]=SPC; PC+=2; STCSGR(int n) /* STC SGR,Rn : Privileged */ R[n]=SGR; PC+=2; STCDBR(int n) /* STC DBR,Rn : Privileged */ R[n]=DBR; PC+=2; STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */ /* m=0–7 */ R[n]=Rm_BANK;...
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STCMVBR(int n) /* STC.L VBR,@-Rn : Privileged */ R[n]–=4; Write_Long(R[n],VBR); PC+=2; STCMSSR(int n) /* STC.L SSR,@-Rn : Privileged */ R[n]–=4; Write_Long(R[n],SSR); PC+=2; STCMSPC(int n) /* STC.L SPC,@-Rn : Privileged */ R[n]–=4; Write_Long(R[n],SPC); PC+=2; STCMSGR(int n) /* STC.L SGR,@-Rn : Privileged */ R[n]–=4;...
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STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */ /* m=0–7 */ R[n]–=4; Write_Long(R[n],Rm_BANK); PC+=2; Possible Exceptions: • General illegal instruction exception • Slot illegal instruction exception • Data TLB miss exception • Data TLB protection violation exception • Address error Rev.
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10.93 STore System register System Control Instruction Store from System Register Execution Format Summary of Operation Instruction Code States T Bit MACH → Rn MACH,Rn 0000nnnn00001010 1 — MACL → Rn MACL,Rn 0000nnnn00011010 1 — PR → Rn PR,Rn 0000nnnn00101010 1 —...
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R[n]–=4; Write_Long(R[n],MACH); PC+=2; STSMMACL(int n) /* STS.L MACL,@-Rn */ R[n]–=4; Write_Long(R[n],MACL); PC+=2; STSMPR(int n) /* STS.L PR,@-Rn */ R[n]–=4; Write_Long(R[n],PR); PC+=2; Possible Exceptions: • Data TLB miss exception • Data TLB protection violation exception • Address error Example ; Before execution R0 = H’FFFFFFFF, MACH = H’00000000 STS MACH,R0 ;...
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10.94 STore from FPU System register System Control Instruction Store from FPU System Register Execution Format Summary of Operation Instruction Code States T Bit FPUL → Rn FPUL,Rn 0000nnnn01011010 1 — FPSCR → Rn FPSCR,Rn 0000nnnn01101010 1 — Rn-4 → Rn, FPUL → (Rn) STS.L FPUL,@-Rn 0100nnnn01010010 1 —...
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PC+=2; Possible Exceptions: • Data TLB miss exception • Data TLB protection violation exception • Address error Examples • STS Example 1: MOV.L #H’12ABCDEF, R12 R12, FPUL FPUL, R13 ; After executing the STS instruction: ; R13 = 12ABCDEF Example 2: FPSCR, R2 ;...
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10.95 SUBtract binary Arithmetic Instruction Binary Subtraction Execution Format Summary of Operation Instruction Code States T Bit Rn-Rm → Rn SUB Rm,Rn 0011nnnnmmmm1000 1 — Description This instruction subtracts the contents of general register Rm from the contents of general register Rn and stores the result in Rn.
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10.96 SUBC SUBtract with Carry Arithmetic Instruction Binary Subtraction with Borrow Execution Format Summary of Operation Instruction Code States T Bit Rn-Rm-T → Rn, borrow → T SUBC Rm,Rn 0011nnnnmmmm1010 1 Borrow Description This instruction subtracts the contents of general register Rm and the T bit from the contents of general register Rn, and stores the result in Rn.
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10.97 SUBV SUBtract with (V flag) underflow check Arithmetic Instruction Binary Subtraction with Underflow Check Execution Format Summary of Operation Instruction Code States T Bit Rn-Rm → Rn, underflow → T SUBV Rm,Rn 0011nnnnmmmm1011 1 Underflow Description This instruction subtracts the contents of general register Rm from the contents of general register Rn, and stores the result in Rn.
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Example ;Before execution R0 = H’00000002, R1 = H’80000001 SUBV R0,R1 ;After execution R1 = H’7FFFFFFF, T = 1 ;Before execution R2 = H’FFFFFFFE, R3 = H’7FFFFFFE SUBV R2,R3 ;After execution R3 = H’80000000, T = 1 Rev. 2.0, 03/99, page 380 of 396...
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10.98 SWAP SWAP register halves Data Transfer Instruction Upper-/Lower-Half Swap Execution Format Summary of Operation Instruction Code States T Bit Rm → lower-2-byte upper-/ SWAP.B Rm,Rn 0110nnnnmmmm1000 1 — lower-byte swap → Rn Rm → upper-/lower-word SWAP.W Rm,Rn 0110nnnnmmmm1001 1 swap →...
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R[n]|=temp; PC+=2; Example ;Before execution R0 = H’12345678 SWAP.B R0,R1 ;After execution R1 = H’12347856 ;Before execution R0 = H’12345678 SWAP.W R0,R1 ;After execution R1 = H’56781234 Rev. 2.0, 03/99, page 382 of 396...
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10.99 Test And Set Logical Instruction Memory Test and Bit Setting Execution Format Summary of Operation Instruction Code States T Bit If (Rn) = 0, 1 → T, else 0 → T TAS.B @Rn 0100nnnn00011011 5 Test result 1 → MSB of (Rn) Description This instruction purges the cache block corresponding to the memory area specified by the contents of general register Rn, reads the byte data indicated by that address, and sets the T bit to 1...
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Possible Exceptions: • Data TLB miss exception • Data TLB protection violation exception • Initial page write exception • Address error Exceptions are checked taking a data access by this instruction as a byte store. Rev. 2.0, 03/99, page 384 of 396...
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10.100 TRAPA TRAP Always System Control Instruction Trap Exception Handling Execution Format Summary of Operation Instruction Code States T Bit imm → TRA, PC+2 → SPC, TRAPA #imm 11000011iiiiiiii 7 — SR → SSR, 1 → SR.MD/ BL/RB, 0x160 → EXPEVT, VBR+H’00000100 →...
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10.101 TST TeST logical Logical Instruction AND Operation T Bit Setting Execution Format Summary of Operation Instruction Code States T Bit Rm,Rn Rn & Rm; if result is 0, 0010nnnnmmmm1000 1 Test 1 → T, else 0 → T result #imm,R0 R0 &...
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TSTM(long i) /* TST.B #imm,@(R0,GBR) */ long temp; temp=(long)Read_Byte(GBR+R[0]); temp&=(0x000000FF & (long)i); if (temp==0) T=1; else T=0; PC+=2; Example ;Before execution R0 = H’00000000 R0,R0 ;After execution T = 1 ;Before execution R0 = H’FFFFFF7F #H’80,R0 ;After execution T = 1 TST.B #H’A5,@(R0,GBR) ;Before execution (R0,GBR) = H’A5 ;After execution T = 0...
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10.102 XOR eXclusive OR logical Logical Instruction Exclusive Logical OR Execution Format Summary of Operation Instruction Code States T Bit Rn ^ Rm → Rn Rm,Rn 0010nnnnmmmm1010 1 — R0 ^ imm → R0 #imm,R0 11001010iiiiiiii 1 — (R0+GBR)^imm → XOR.B #imm,@(R0,GBR) 11001110iiiiiiii 4 —...
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Write_Byte(GBR+R[0],temp); PC+=2; Example ;Before execution R0 = H’AAAAAAAA, R1 = H’55555555 R0,R1 ;After execution R1 = H’FFFFFFFF ;Before execution R0 = H’FFFFFFFF #H’F0,R0 ;After execution R0 = H’FFFFFF0F XOR.B #H’A5,@(R0,GBR) ;Before execution (R0,GBR) = H’A5 ;After execution (R0,GBR) = H’00 Rev.
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10.103 XTRCT eXTRaCT Data Transfer Instruction Middle Extraction from Linked Registers Execution Format Summary of Operation Instruction Code States T Bit Middle 32 bits of Rm:Rn → Rn XTRCT Rm,Rn 0010nnnnmmmm1101 1 — Description This instruction extracts the middle 32 bits from the 64-bit contents of linked general registers Rm and Rn, and stores the result in Rn.
Page 405: Appendix A Address List

Appendix A Address List Table A.1 Address List Synchro- Area 7 Power-On Manual nization Address* Reset Reset Module Register P4 Address Size Sleep Standby Clock PTEH H’FF00 0000 H’1F00 0000 32 Undefined Undefined Held Held Iclk PTEL H’FF00 0004 H’1F00 0004 32 Undefined Undefined Held...
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Table A.1 Address List (cont) Synchro- Area 7 Power-On Manual nization Module Register P4 Address Address* Size Reset Reset Sleep Standby Clock H’FF80 0014 H’1F80 0014 32 H’0000 0000 Held Held Held Bclk H’FF80 0018 H’1F80 0018 16 H’0000 Held Held Held Bclk...
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Table A.1 Address List (cont) Synchro- Area 7 Power-On Manual nization Module Register P4 Address Address* Size Reset Reset Sleep Standby Clock FRQCR H’FFC0 0000 H’1FC0 0000 16 Held Held Held Pclk STBCR H’FFC0 0004 H’1FC0 0004 8 H’00 Held Held Held Pclk...
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Rev. 2.0, 03/99, page 394 of 396...
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SCSPTR2 H’FFE8 0020 H’1FE8 0020 16 H’0000* H’0000* Held Held Pclk SCIF SCLSR2 H’FFE8 0024 H’1FE8 0024 16 H’0000 H’0000 Held Held Pclk Hitachi- SDIR H’FFF0 0000 H’1FF0 0000 16 H’FFFF* Held Held Held Pclk Hitachi- SDDR H’FFF0 0008 H’1FF0 0008 32 Held Held Held...
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2. Includes undefined bits. See the descriptions of the individual modules. 3. Use word-size access when writing. Perform the write with the upper byte set to H’5A or H’A5, respectively. Byte- and longword-size writes cannot be used. Use byte-size access when reading. Rev.
Page 411: Appendix B Instruction Prefetch Side Effects

Appendix B Instruction Prefetch Side Effects The SH4 is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. Therefore, program code must not be located in the last 20-byte area of any memory space. If program code is located in these areas, the memory area will be exceeded and a bus access for instruction pre-reading may be initiated.
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Publication Date: 1st Edition, August 1998 2nd Edition, March 1999 Published by: Electronic Devices Sales & Marketing Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.