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Table E.1
Pin States in Reset, Power-Down State, and Bus-Released State (cont)
Signal Name
I/O
WE2/CAS2/DQM2
O
WE1/CAS1/DQM1
O
WE0/CAS0/DQM0
O
DACK1–DACK0
O
MD7/TXD
I/O
MD6/IOIS16
I
I/O *
MD5/RAS2
I/O *
MD4/CE2B
I/O *
MD3/CE2A
CKIO
O
STATUS1–
O
STATUS0
IRL3–IRL0
I
NMI
I
DREQ1–DREQ0
I
DRAK1–DRAK0
O
MD0/SCK
I/O
RXD
I
SCK2/MRESET
I
MD1/TXD2
I/O
MD2/RXD2
I
CTS2
I/O
MD8/RTS2
I/O
TCLK
I/O
TDO
O
TMS
I
TCK
I
TDI
I
TRST
I
10
CKIO2 *
O
Rev. 6.0, 07/02, page 952 of 986
Reset
(Power-On)
Master Slave
16
Z *
H
Z *
16
H
16
Z *
H
L
L
I *
16
I *
16
16
16
I *
I *
1
16
16
I *
I *
2
16
16
I *
I *
3
16
16
I *
I *
O
O
O
O
16
16
PI *
PI *
16
16
PI *
PI *
16
16
PI *
PI *
L
L
16
16
I *
I *
16
16
PI *
PI *
16
16
PI *
PI *
16
16
I *
I *
16
16
I *
I *
16
16
PI *
PI *
I *
16
I *
16
PI *
16
PI *
16
O
O
PI *
16
PI *
16
16
16
PI *
PI *
16
16
PI *
PI *
PI *
16
PI *
16
O
O
Reset
(Manual)
Master Slave
Standby
6
14
14
O *
Z *
Z *
O *
O *
6
Z *
14
Z *
14
O *
6
14
14
O *
Z *
Z *
O *
12
Z *
O *
L
L
Z *
12
Z *
12
Z *
12
O *
13
13
13
I *
I *
I *
13
6
13
13
Z *
O *
Z *
Z *
O *
13
13
13
Z *
Z *
Z *
H *
H
13
13
13
Z *
Z *
Z *
H *
H
11
11
11
ZO *
ZO *
ZO *
O
O
O
13
13
13
I *
I *
I *
13
13
13
I *
I *
I *
12
12
12
I *
I *
I *
12
Z *
O *
L
L
12
12
12
I *
I *
I *
Z *
12
12
12
I *
I *
I *
12
12
12
I *
I *
I *
12
12
12
Z *
Z *
Z *
O *
12
12
12
I *
I *
I *
12
12
12
I *
I *
I *
Z *
I *
12
I *
12
I *
12
Z *
I *
12
I *
12
I *
12
O
O
O
O
I *
16
I *
16
I *
16
16
16
16
I *
I *
I *
16
16
16
I *
I *
I *
I *
16
I *
16
I *
16
11
11
11
ZO *
ZO *
ZO *
Hard-
Bus
ware
Released
Standby Notes
5
14
5
Z *
O *
Z
5
Z *
14
O *
5
Z
5
14
5
Z *
O *
Z
8
12
O *
Z
8
Z *
12
O
Z
13
I *
I
5
13
5
Z *
O *
Z
7
13
Z *
Z
7
13
Z *
Z
11
ZO *
Z
18
Z *
O
13
I *
I
13
I *
I
12
I *
I
8
12
O *
Z
12
8
12
O *
I *
O
Z
12
I *
I
12
I *
I
8
12
Z *
O
Z
12
I *
I
12
8
12
O *
I *
O
Z
12
O *
8
I *
12
O
Z
I *
12
O
Z
O
Z
I *
16
I
16
I *
I
16
I *
I
I *
16
I
11
ZO *
Z
DMAC
SCI
PCMCIA
(I/O)
DRAM2
PCMCIA
PCMCIA
INTC
INTC
DMAC
DMAC
SCI
SCI
SCIF
SCIF
SCIF
SCIF
SCIF
TMU
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
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