Peripheral Module Signal Timing; Table 22.36 Peripheral Module Signal Timing (1) - Hitachi SH7750 Hardware Manual

22.3.4

Peripheral Module Signal Timing

Table 22.36 Peripheral Module Signal Timing (1)

Module Item Symbol
TMU, Timer clock t
RTC pulse width
(high)
Timer clock t
pulse width
(low)
Timer clock t
rise time
Timer clock t
fall time
Oscillation t
settling time
SCI Input clock t
cycle (asyn-
chronous)
t
Input clock
cycle (syn-
chronous)
Input clock t
pulse width
Input clock t
rise time
Input clock t
fall time
t
Transfer data
delay time
Receive data t
setup time
(synchronous)
Receive data t
hold time
(synchronous)
Rev. 6.0, 07/02, page 924 of 986
HD6417750 HD6417750
RBP240 RBP200
2
*
Min Max Min
4 — 4
TCLKWH
4 — 4
TCLKWL
— 0.8 —
TCLKr
— 0.8 —
TCLKf
— 3 —
ROSC
4 — 4
Scyc
6 — 6
Scyc
0.4 0.6 0.4
SCKW
— 0.8 —
SCKr
— 0.8 —
SCKf
1.5 5.3 1.5
TXD
16 — 16
RXS
16 — 16
RXH
HD6417750 HD6417750
RF240 RF200
2 2
* *
Max Min Max Min
— 4 — 4
— 4 — 4
0.8 — 0.8 —
0.8 — 0.8 —
3 — 3 —
— 4 — 4
— 6 — 6
0.6 0.4 0.6 0.4
0.8 — 0.8 —
0.8 — 0.8 —
6 1.5 6 1.5
— 16 — 16
— 16 — 16
2
*
Max Unit Figure
Pcyc * 1
— 22.61
1
Pcyc *
— 22.61
1
Pcyc *
0.8 22.61
Pcyc * 1
0.8 22.61
3 s 22.62
Pcyc * 1
— 22.63
1
Pcyc *
— 22.63
0.6 t 22.63
Scyc
Pcyc * 1
0.8 22.63
1
Pcyc *
0.8 22.63
6 ns 22.64
— ns 22.64
— ns 22.64