Hitachi SH7750 Hardware Manual page 39

Figure 14.1 Block Diagram of DMAC................................................................................ 492
Figure 14.2 DMAC Transfer Flowchart.............................................................................. 511
Figure 14.3 Round Robin Mode.......................................................................................... 516
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode ........................ 517
Figure 14.5 Data Flow in Single Address Mode ................................................................. 519
Figure 14.6 DMA Transfer Timing in Single Address Mode ............................................. 520
Figure 14.7 Operation in Dual Address Mode .................................................................... 521
Figure 14.8 Example of Transfer Timing in Dual Address Mode....................................... 522
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode............................................. 523
Figure 14.10 Example of DMA Transfer in Burst Mode ...................................................... 523
Figure 14.11 Bus Handling with Two DMAC Channels Operating ..................................... 527
Dual Address Mode/Cycle Steal Mode External Bus → External Bus/
Figure 14.12
DREQ (Level Detection), DACK (Read Cycle) .............................................. 530
Dual Address Mode/Cycle Steal Mode External Bus → External Bus/
Figure 14.13
DREQ (Edge Detection), DACK (Read Cycle) ............................................... 531
Dual Address Mode/Burst Mode External Bus → External Bus/
Figure 14.14
DREQ (Level Detection), DACK (Read Cycle) .............................................. 532
Dual Address Mode/Burst Mode External Bus → External Bus/
Figure 14.15
DREQ (Edge Detection), DACK (Read Cycle) ............................................... 533
Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) →
Figure 14.16
External Bus..................................................................................................... 534
Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI
Figure 14.17
(Level Detection) ............................................................................................. 535
Single Address Mode/Cycle Steal Mode External Bus → External Bus/
Figure 14.18
DREQ (Level Detection) ................................................................................. 536
Single Address Mode/Cycle Steal Mode External Bus → External Bus/
Figure 14.19
DREQ (Edge Detection) .................................................................................. 537
Single Address Mode/Burst Mode External Bus → External Bus/
Figure 14.20
DREQ (Level Detection) ................................................................................. 538
Single Address Mode/Burst Mode External Bus → External Bus/
Figure 14.21
DREQ (Edge Detection) .................................................................................. 539
Single Address Mode/Burst Mode External Bus → External Bus/
Figure 14.22
DREQ (Level Detection)/32-Byte Block Transfer
(Bus Width: 64 Bits, SDRAM: Row Hit Write) .............................................. 540
Figure 14.23 On-Demand Transfer Mode Block Diagram.................................................... 545
Figure 14.24 System Configuration in On-Demand Data Transfer Mode ............................ 547
Figure 14.25 Data Transfer Request Format ......................................................................... 548
Single Address Mode: Synchronous DRAM → External Device Longword
Figure 14.26
Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01,
CAS latency = 3, TPC[2:0] = 001) ...................................................................... 551
Single Address Mode: External Device → Synchronous DRAM Longword
Figure 14.27
Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01,
TRWL[2:0] = 101, TPC[2:0] = 001).................................................................... 552
Rev. 6.0, 07/02, page xxxix of I