Hitachi SH7750 Hardware Manual page 352

Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt
generation when the UNF status flag is set to 1, indicating TCNT underflow.
Bit 5: UNIE
0
1
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the external clock input
edge when an external clock is selected or the input capture function is used in channels 0 to 2.
Bit 4: CKEG1 Bit 3: CKEG0
0 0
1
1 X
Note: X: 0 or 1 (don't care)
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): These bits select the TCNT count clock.
With channels 0 to 2, when the on-chip RTC output clock is selected as the count clock for a
channel, that channel can operate even in module standby mode. When another clock is selected,
the channel does not operate in standby mode.
Bit 2: TPSC2 Bit 1: TPSC1
0 0
1
1 0
1
Rev. 6.0, 07/02, page 302 of 986
Description
Interrupt due to underflow (TUNI) is not enabled
Interrupt due to underflow (TUNI) is enabled
Description
Count/input capture register set on rising edge
Count/input capture register set on falling edge
Count/input capture register set on both rising and falling edges
Bit 0: TPSC0
0
1
0
1
0
1
0
1
Description
Counts on Pφ/4
Counts on Pφ/16
Counts on Pφ/64
Counts on Pφ/256
Counts on Pφ/1024
Reserved (Do not set)
Counts on on-chip RTC output clock
(Do not set this pattern for channel 3 or 4)
Counts on external clock
(Do not set this pattern for channel 3 or 4)
(Initial value)
(Initial value)
(Initial value)