Hitachi SH7750 Hardware Manual page 616

Sh7750 series superh risc engine
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CLK
A25–A0
D63–D0
RAS,
CAS, WE
ID1, ID0
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Rev. 6.0, 07/02, page 566 of 986
DTR
ID = 1, 2, or 3
Request to Channels 1–3 Using Data Bus
RA
CA
BA
RD
D0
D1
D2
D3
01 or 10 or 11

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