Hitachi SH7750 Hardware Manual page 628

Table 14.13 Register Configuration (cont)
Chan-
nel Name
4 DMA source
address register 4
DMA destination
address register 4
DMA transfer
count register 4
DMA channel
control register 4
5 DMA source
address register 5
DMA destination
address register 5
DMA transfer
count register 5
DMA channel
control register 5
6 DMA source
address register 6
DMA destination
address register 6
DMA transfer
count register 6
DMA channel
control register 6
7 DMA source
address register 7
DMA destination
address register 7
DMA transfer
count register 7
DMA channel
control register 7
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
*1 Bit 1 of CHCR0–CHCR7 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
*2 In the SH7750R, writes from the CPU and writes from external I/O devices using the
DTR format are possible in DDT mode.
Rev. 6.0, 07/02, page 578 of 986
Abbre- Read/
viation Write Initial Value P4 Address
SAR4 R/W Undefined
DAR4 R/W Undefined
DMATCR4 R/W Undefined
1
R/W *
CHCR4 H'00000000 H'FFA0005C H'1FA0005C 32
SAR5 R/W Undefined
DAR5 R/W Undefined
DMATCR5 R/W Undefined
1
R/W *
CHCR5 H'00000000 H'FFA0006C H'1FA0006C 32
SAR6 R/W Undefined
DAR6 R/W Undefined
DMATCR6 R/W Undefined
1
R/W *
CHCR6 H'00000000 H'FFA0007C H'1FA0007C 32
SAR7 R/W Undefined
DAR7 R/W Undefined
DMATCR7 R/W Undefined
1
R/W *
CHCR7 H'00000000 H'FFA0008C H'1FA0008C 32
Area 7
Address
H'FFA00050 H'1FA00050 32
H'FFA00054 H'1FA00054 32
H'FFA00058 H'1FA00058 32
H'FFA00060 H'1FA00060 32
H'FFA00064 H'1FA00064 32
H'FFA00068 H'1FA00068 32
H'FFA00070 H'1FA00070 32
H'FFA00074 H'1FA00074 32
H'FFA00078 H'1FA00078 32
H'FFA00080 H'1FA00080 32
H'FFA00084 H'1FA00084 32
H'FFA00088 H'1FA00088 32
Access
Size