Hitachi SH7750 Hardware Manual page 644

 Synchronous mode
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other chips that have a synchronous communication function.
There is a single serial data transfer format.
Data length:
Receive error detection: Overrun errors
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected.
•
Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Four interrupt sources
There are four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and
receive-error—that can issue requests independently. The transmit-data-empty interrupt and
receive-data-full interrupt can activate the DMA controller (DMAC) to execute a data transfer.
• When not in use, the SCI can be stopped by halting its clock supply to reduce power
consumption.
Rev. 6.0, 07/02, page 594 of 986
8 bits