Hitachi SH7750 Hardware Manual page 700

Sh7750 series superh risc engine
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Start of transmission/reception
Read TDRE flag in SCSSR1
No
Write transmit data
to SCTDR1 and clear TDRE flag
in SCSSR1 to 0
Read ORER flag in SCSSR1
Read RDRF flag in SCSSR1
No
Read receive data in SCRDR1,
and clear RDRF flag
in SCSSR1 to 0
No
All data transferred?
Clear TE and RE bits
in SCRSR1 to 0
End of transmission/reception
Note: When switching from transmit or receive operation to simultaneous transmit and receive
operations, first clear the TE bit and RE bit to 0, then set both these bits to 1.
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception
Rev. 6.0, 07/02, page 650 of 986
TDRE = 1?
Yes
ORER = 1?
No
RDRF = 1?
Yes
Yes
1. SCI status check and transmit data
write:
Read SCSSR1 and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR1 and clear
the TDRE flag to 0. Transition of the
TDRE flag from 0 to 1 can also be
identified by a TXI interrupt.
2. Receive error handling:
If a receive error occurs, read the
ORER flag in SCSSR1 , and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
3. SCI status check and receive data
read:
Read SCSSR1 and check that the
RDRF flag is set to 1, then read the
receive data in SCRDR1 and clear the
Yes
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
Error handling
identified by an RXI interrupt.
4. Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, finish reading the RDRF
flag, reading SCRDR1, and clearing
the RDRF flag to 0, before the MSB
(bit 7) of the current frame is received.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR1 and clear the TDRE flag to
0.
(Checking and clearing of the TDRE
flag is automatic when the DMAC is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to SCTDR1. Similarly, the
RDRF flag is cleared automatically
when the DMAC is activated by a
receive-data-full interrupt (RXI)
request and the SCRDR1 value is
read.)

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