Figure 8.1 Basic Pipelines - Hitachi SH7750 Hardware Manual

1. General Pipeline
I
• Instruction fetch • Instruction
2. General Load/Store Pipeline
I
• Instruction fetch • Instruction
3. Special Pipeline
I
• Instruction fetch • Instruction
4. Special Load/Store Pipeline
I
• Instruction fetch • Instruction
5. Floating-Point Pipeline
I
• Instruction fetch • Instruction
6. Floating-Point Extended Pipeline
I
• Instruction fetch • Instruction
7. FDIV/FSQRT Pipeline
Rev. 6.0, 07/02, page 194 of 986
D
• Operation
decode
• Issue
• Register read
• Destination address calculation
for PC-relative branch
D
• Address
decode calculation
• Issue
• Register read
D
• Operation
decode
• Issue
• Register read
D
• Address
decode calculation
• Issue
• Register read
D
• Computation 1
decode
• Issue
• Register read
D
• Computation 0
decode
• Issue
• Register read
Computation: Takes several cycles

Figure 8.1 Basic Pipelines

NA
EX
• Non-memory
data access
EX MA
• Memory
data access
NA
SX
• Non-memory
data access
MA
SX
• Memory
data access
F2
F1
• Computation 2
F0 F1
• Computation 1
F3
S
• Write-back
S
• Write-back
S
• Write-back
S
• Write-back
FS
• Computation 3
• Write-back
F2 FS
• Computation 2 • Computation 3
• Write-back