Table 14.13 Register Configuration - Hitachi SH7750 Hardware Manual

Table 14.13 Register Configuration

Chan-
nel Name
0 DMA source
address register 0
DMA destination
address register 0
DMA transfer
count register 0
DMA channel
control register 0
1 DMA source
address register 1
DMA destination
address register 1
DMA transfer
count register 1
DMA channel
control register 1
2 DMA source
address register 2
DMA destination
address register 2
DMA transfer
count register 2
DMA channel
control register 2
3 DMA source
address register 3
DMA destination
address register 3
DMA transfer
count register 3
DMA channel
control register 3
Com- DMA operation
mon register
Abbre- Read/
viation Write Initial Value P4 Address
2
R/W *
SAR0 Undefined
2
R/W *
DAR0 Undefined
2
DMATCR0 R/W *
Undefined
1 2
R/W * *
CHCR0 H'00000000 H'FFA0000C H'1FA0000C 32
SAR1 R/W Undefined
DAR1 R/W Undefined
DMATCR1 R/W Undefined
1
R/W *
CHCR1 H'00000000 H'FFA0001C H'1FA0001C 32
SAR2 R/W Undefined
DAR2 R/W Undefined
DMATCR2 R/W Undefined
1
R/W *
CHCR2 H'00000000 H'FFA0002C H'1FA0002C 32
SAR3 R/W Undefined
DAR3 R/W Undefined
DMATCR3 R/W Undefined
1
R/W *
CHCR3 H'00000000 H'FFA0003C H'1FA0003C 32
1
R/W *
DMAOR H'00000000 H'FFA00040 H'1FA00040 32
Area 7
Address
H'FFA00000 H'1FA00000 32
H'FFA00004 H'1FA00004 32
H'FFA00008 H'1FA00008 32
H'FFA00010 H'1FA00010 32
H'FFA00014 H'1FA00014 32
H'FFA00018 H'1FA00018 32
H'FFA00020 H'1FA00020 32
H'FFA00024 H'1FA00024 32
H'FFA00028 H'1FA00028 32
H'FFA00030 H'1FA00030 32
H'FFA00034 H'1FA00034 32
H'FFA00038 H'1FA00038 32
Rev. 6.0, 07/02, page 577 of 986
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