Figure 22.66(B) Dbreq/Tr Input Timing And Bavl Output Timing - Hitachi SH7750 Hardware Manual

CKIO
DBREQ
BAVL
TR
D63 to D0
(READ)
Figure 22.66(b) DBREQ
1/2V
Note: When clock is input from TCK pin
SCK2/
(High)
/
BRKACK
Rev. 6.0, 07/02, page 932 of 986
t t
DBQS DBQH
t
BAVD
(1): [2CKIO cycle – t
(2): DTR = 1CKIO cycle (= 10 ns: 100 MHz)
(t
DTRS
DBREQ/TR TR Input Timing and BAVL
DBREQ DBREQ TR TR
t
TCKH
V
IH
DDQ
Figure 22.67 TCK Input Timing
t t
ASEBRKS ASEBRKH
Figure 22.68 RESET
t
BAVD
t
TRS
t
DTRS
(2)
(1)
] (= 18 ns: 100 MHz)
DTRS
+ t ) < DTR < 10 ns
DTRH
BAVL Output Timing
BAVL BAVL
t
TCKcyc
t
TCKL
V
IH
V V
IL
t
TCKf
(Low)
RESET Hold Timing
RESET RESET
t
TRH
t
DTRH
V
IH
1/2V
DDQ
IL
t
TCKr
t
t
ASEBRKS
ASEBRKH