Hitachi SH7750 Hardware Manual page 8

Section
9.8.5 Hardware Standby
Mode Timing (SH7750S,
SH7750R Only)
10.2.1 Block Diagram of
CPG
10.2.2 CPG Pin
Configuration
10.2.3 CPG Register
Configuration
10.3 Clock Operating Modes
10.8.2 Watchdog Timer
Control/Status Register
(WTCSR)
10.10 Notes on Board
Design
11.1.1 Features
11.1.2 Block Diagram
11.1.3 Pin Configuration
11.1.4 Register Configuration 270
Rev. 6.0, 07/02, page viii of I
Page Item
244 to Figures 9.12, 9.13, 9.15
246
249 Figure 10.1 (1) Block
Diagram of CPG (SH7750,
SH7750S)
250 Figure 10.1 (2) Block
Diagram of CPG (SH7750R)
252 Table 10.1 CPG Pins
252 Table 10.2 CPG Register
253 Table 10.3 (1) Clock
Operating Modes (SH7750,
SH7750S)
253 Table 10.3 (2) Clock
Operating Modes (SH7750R)
254 Table 10.4 FRQCR Settings
and Internal Clock
Frequencies
261
265 When Using a PLL Oscillator
Circuit
266 Figure 10.5 Points for
Attention when Using PLL
Oscillator Circuit
267
268 Figure 11.1 Block Diagram
of RTC
269 Table 11.1 RTC Pins
Table 11.2 RTC Registers
Description
Figures changed
Notes added
Amended
Newly added
Table and Note
amended
Description added
Description added and
amended
Table amended and
Note amended and
added
Newly added
Table and Note
amended
Description amended
Description amended
Amended
Description added for
Alarm interrupts
Figure amended and
Note added
Table amended
RTC control register 3
and Year alarm register
added to table, and
Note added