Hitachi SH7750 Hardware Manual page 532

Sh7750 series superh risc engine

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D63–D0 (write)

D63–D0 (write)

Rev. 6.0, 07/02, page 482 of 986

Asserted for at least 2 cycles

Master mode device access

Must be asserted for

at least 2 cycles

Slave mode device access

Master access

Figure 13.78 Arbitration Sequence

Negated within 2 cycles

Must be negated within 2 cycles

Slave access

Master access

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