Hitachi SH7750 Hardware Manual page 398

• When DRAM or Synchronous DRAM Interface is Set*
Bit 11: A2W2 Bit 10: A2W1
0 0
1
1 0
1
Notes: *1 External wait input is always ignored.
*2 RAS down mode is prohibited.
Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states
to be inserted for area 1. For details on MPX interface setting, see table 13.6, MPX Interface is
Selected (Areas 0 to 6).
Bit 8: A1W2 Bit 7: A1W1
0 0
1
1 0
1
Rev. 6.0, 07/02, page 348 of 986
DRAM CAS
Bit 9: A2W0 Assertion Width
0 1
1 2
0 3
1 4
0 7
1 10
0 13
1 16
Bit 6: A1W0 Inserted Wait States
0 0
1 1
0 2
1 3
0 6
1 9
0 12
1 15 (Initial value)
1
Description
CAS
CAS CAS
Synchronous DRAM
CAS Latency Cycles CAS
CAS CAS
Inhibited
2
1 *
2
3
2
4 *
2
5 *
Inhibited
Inhibited
Description
RDY Pin RDY
RDY RDY
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled